SAN JOSE--Hitachi Ltd. and STMicroelectronics this week plan to disclose details of a jointly-developed 64-bit RISC microprocessor architecture, called the SH-5, which is expected to be introduced next year for cost-sensitive consumer and multimedia applications.
At the Microprocessor Forum here on Wednesday, the two companies said they will present the first details of the new RISC architecture, which has been designed to maintain software compatibility with Hitachi's SH-4 software but extend the performance with 64-bit data bandwidth. The SH-5 project was launched in late 1997 as part of broader agreement giving STMicroelectronics licenses to Hitachi's SH-3 and SH-4 processors (see Dec. 9, 1997 story).
Aimed at embedded processing applications, the 64-bit SH-5 core will deliver 714 million instructions per second (MIPS) while consuming 600 mW at a 400-MHz clock frequency and 1.5-volt power supply, according to Hitachi and STMicroelectronics. (The performance is based on Dhrystone 1.1 benchmarks and 604 MIPS Dhrystone 2.1.) The development team said the device will provide up to 9.6 billion operations per second and 1.6 billions of multiply-accumulate operations per second for applications requiring digital signal processing, or DSP-like, computing.
The partners said the SH-5 was developed with shared engineering units in San Jose, STMicroelectronics' facility in Bristol, England, and Hitachi's operation in Tokyo. Samples of evaluation units based on the SH-5 core are scheduled to become available in the second half of 2000.
Hitachi plans to produce chips with SH-5 cores at its fab in Naka, Japan, while STMicroelectronics said it will manufacture ICs with the 64-bit RISC architecture in Crolles, France. The companies said these chips will compete in cost-sensitive applications when they reach high-volume shipments.
Among the applications being targeted for SH-5 products are home networking, residential gateways, digital TV, set-top boxes, in-vehicle navigation, and processing-intensive multimedia/video applications as well as high-end portable products. The first central processing unit will be specified at 400 MHz and produced in 0.15-micron technology, according to the two companies.