SAN JOSE--Introducing a new and final step in the deep-submicron design process, Numerical Technologies Inc. this week launched "silicon-vs.-layout" checking tool, called SiVL. NumeriTech said this kind of checking tool is needed to ensure that layouts at 0.18 micron and below will match the actual silicon.
SiVL compares a GDSII layout file to a simulated image of the actual manufactured silicon for a particular process. It's needed because once processes reach 0.18 micron, features are smaller than the wavelength of the optical source that will be used to produce them, NumeriTech said. With such chips, the end silicon does not look like the photomask or the layout.
Many chip manufacturers and designers have started to use optical proximity correction (OPC), or phase shifting, to make slight modifications to the layout in order to obtain the desired silicon. But designers don't necessarily know when or where OPC is needed--and that's where SiVL comes in.
"What this tool does, very accurately and very fast, is generate what the silicon will look like for a particular process for any given layout," said Atul Sharan, vice president of marketing at NumeriTech in San Jose. "It tells you whether you need OPC, and most important, after you run OPC, tells you whether it worked."
SiVL is a "first of its kind" type of tool, Sharan said, aimed at both chip designers and foundries. "We believe the last step of the design flow will be an outgoing check to determine whether the design intent meets silicon or not," he said. "Eventually it should end up on the desk of every designer who's doing subwavelength geometries."
As such, he said, silicon-vs.-layout checking is analogous to design rule checking and layout-vs.-schematic checking, both of which have moved to designers' desks as essential applications before going to silicon.
Although OPC tools are available from NumeriTech and other companies, there's a problem with them--they "apply OPC globally everywhere," Sharan said. This in turn creates problems in mask-making and overall yield. SiVL, on the other hand, allows "just enough OPC," Sharan said.
SiVL takes a GDSII file as input and, with its support for hierarchy, has handled files as large as 0.5 Gbyte, said Michael Sanie, NumeriTech's director of product marketing. SiVL also needs calibrated process models.
These models have two parts: one that represents optical effects and one that represents mechanical effects, such as etch and photoresist.
At present, the calibrated process models typically come from NumeriTech's work with a given fab. "An accurate calibrated model can be done in hours, and our goal is to make them widely available," Sharan said. The same models are used for NumeriTech's Virtual Stepper mask inspection software, which is embedded in mask inspection tools from Applied Materials, KLA-Tencor and Zygo.
SiVL contains a simulation engine that applies the process model to the layout. The outputs include an error file that shows which portions of the silicon will not match the layout, and a visual image of the GDSII file. SiVL can be rerun after OPC is applied to check its effectiveness. SiVL models can also be used with NumeriTech's "iN-phase" phase-shifting product, announced earlier this year (see May 3 story).
NumeriTech promises that the product is fast and easy to use. In one test case, Sanie said, SiVL ran a 276-Mbyte GDSII file in two hours and two minutes on a Windows NT platform. The product can be used for full chips or blocks.
SiVL is available now on Unix and Windows NT platforms starting at $195,000.