BERKELEY, Calif. ( ChipWire) -- A joint effort between Hitachi Ltd.'s Central Research Laboratory in Tokyo and researchers at the University of California at Berkeley is homing in on a robust CMOS transistor that could operate at 25-nanometer (0.025-micron) gate lengths. The new gate geometry, which could solve the short-channel effects that threaten to disrupt field-effect transistor designs below 0.1-micron design rules, will be revealed at the International Electron Devices Meeting early next month.
The basic technique is to grow a thin vertical silicon "fin" that stretches over larger-area source and drain regions. Once the fin is defined, silicon-germanium gate electrode material can be deposited so that it surrounds the fin on both sides, creating a double gate structure. That geometry gives the gate more control over current flow at short distances between source and drain.
Last year, the group reported an NMOS transistor using the technique. In the meantime, the researchers have created a PMOS version, which is being reported at this year's IEDM. The next step will be to combine the two processes to create a true CMOS transistor that could function in ultradense circuits.
As devices shrink in size, transistor designers are faced with the problem of shortening distances between the source and drain regions. Since the channel between these two regions is used to gate electron flow, the electric field at the ends of a short channel begins to disrupt the control exerted by the field on the gate. The vertical fin structure has shown how this problem can be controlled.
The report will show good transistor IV curves for a number of devices with channel lengths below 30 nm. Surprisingly, the operating voltages can be as high as 1.5 volts, bringing the technology into the region of current IC operating voltages.