COLORADO SPRINGS, Colo. ( ChipWire/EET) -- A wholesale move to off-the-shelf processors, system buses and high-volume manufacturing disciplines is sweeping the satellite industry. At the U.S. Space Foundation's second annual Core Technologies for Space Systems conference this week, proprietary and Defense Department buses and CPUs took a backseat to CompactPCI and radiation-hardened PowerPC, X86 and TMS320 processors.
The drive to cost-efficient design comes at a time of deep economic uncertainty in the satellite community. The bankruptcy declarations of satellite voice providers Iridium LLC and ICO Global Communications have sent a chill down the industry's collective spine, even as the first data ventures prepare to lift off.
In a keynote speech here, NASA chief engineer Dan Mulville said that cost reduction remains a prime goal for the civilian space agency, regardless of the twists and turns of commercial space efforts. In fact, NASA wants to challenge contractors to move a step beyond the "fast and cheap" subsystem goals of the current planetary missions, Mulville said.
Failures in Mars missions show that NASA and contractors must put higher quality control front and center, he said. But deep-space missions of the future will also require a new level of technology "focusing on how we build intelligence into the system." This includes integrating micromachined elements, microminiature sensors and fault-tolerant software into less costly systems, Mulville said, to make unmanned deep-space missions autonomous, resilient, reconfigurable and highly distributed in intelligence.
The current mania for small satellites and picosatellites will drive another notch in integration, he predicted, as developers look at "nanosatellite clusters" that borrow concepts from terrestrial microminiature unmanned aerial vehicles. The wealth of process-shrunk 32- and 64-bit processors, as well as new concepts for master/slave processors, will give the nanosatellite developers plenty of options to work with, Mulville said.
Developers of the current generation of small satellites are happy just to move to processors and buses the earthbound commercial world takes for granted. Lockheed-Martin Space Electronics & Communications, based in Manassas, Va., which licensed the PowerPC 750 architecture from IBM Corp. a year ago, has moved beyond design of a rad-hard MPU and is in the final stages of designing a PowerPC bridge chip, interfacing the RISC processor to a PCI bus.
Early next year, Lockheed-Martin will begin offering a standard CompactPCI development board using both the RAD750 design and a rad-hard PowerPC, said program manager Robert Delean. Delean said developers are asking for CompactPCI across the board, and Lockheed-Martin has tried to make it easy for those with satellites based on a rad-hard RS6000 processor to easily upgrade to RAD750.
For its part, Space Electronics Inc. (SEI) has a tiered program for using Intel architecture designs. The company won a contract to provide the peripheral chips and board-level design for a rad-hard version of the Pentium that Sandia National Labs began developing nearly two years ago. But Norman Hall, program manager at SEI, of San Diego, said that Sandia has pushed out its development schedule for the Pentium.
To address nearer-term customer needs, Space Electronics began examining older Intel parts, and learned that a lot of the 486DX processors produced had good rad-tolerant specs.
SEI bought all the 486DX die it could get, and tucks them in a special RadPack package, surrounded by latch-up protection circuitry. For many satellites with requirements in the 100-kilorad region, the 486 product proves sufficient, Hall said. Meanwhile, the company is examining single-board computer development using rad-hard PowerPC 750 and 603 processors as alternatives to the Pentium.
As space developers move from discrete multiply-accumulates and barrel shifters in older designs to advanced algorithm support, the shift to programmable DSPs is being undertaken both in satellites and in ground-based range support. Here, Texas Instruments Inc.'s TMS320 architecture is a clear favorite.
Seakr Engineering Inc., an Englewood, Colo., company that makes specialized solid-state recorders for civilian and military spacecraft, has turned to near-universal use of dual- and quad-DSP systems for data acquisition. Tom Webb, applications engineer at Seakr, described such a system being developed for Warfighter-1, a special Air Force Research Lab experiment that will ride on Orbital Image Corp.'s Orbview-4, slated for a 2000 launch.
Warfighter-1 is testing various concepts for hyperspectral-image analysis for next-generation communication and intelligence platforms. Seakr has designed a recorder in which rad-tolerant TMS320C40s and Actel 14100 FPGAs are used in parallel systems, controlled by a common 1750A processor. By using both the 1750 bus and a dedicated memory bus, the parallel DSP implementation can meet most near-real-time data acquisition requirements, the company said.
NASA is shifting to programmable DSPs for ground-based ranging stations, said Scott Bryant of NASA's Jet Propulsion Laboratory. Earlier ranging stations had embarrassingly low levels of integration, because the DSPs of the late 1980s couldn't keep up with the FIFO buffers NASA used in earlier systems. Bryant said that after JPL performed a breadboard test in 1998 showing that 120-MHz commercial DSPs could keep pace with 16-MHz FIFOs, the agency immediately turned to programmable options. A dedicated rack that held the former Sequential Ranging Assembly and its controller is now replaced by four VME boards, two using off-the-shelf Pentek systems based on the TMS320C6201.
On the memory front, Ron Hehr, CAM-Engine marketing director at UTMC Microelectronic Systems in Colorado Springs, urged developers to consider content-addressable memories. CAMs offer fast table lookups, serving both Layer 3 switching handled across intersatellite links, and fast image identifiers for imaging satellites, Hehr said.
UTMC considered developing dedicated rad-hard CAMs, but decided they would not scale to be cost-effective for commercial space missions, he added. Instead, it designed a special controller, the UTCAM-Engine, to be used with existing rad-hard SRAMs and SDRAMs.
The controller lets the host view blocks of traditional RAM, up to 32 Gbytes in size, as CAM tables. The ability to scale to large sizes would allow satellite networks to serve as space-based routers, Hehr said. In image matching, the search engine becomes a "proximity match engine," looking for pixel-shift image variants to identify patterns when used with fuzzy-logic subsystems.
Wade Molnau, of Motorola Space Systems' systems solutions group in Scottsdale, Ariz., described to the conference the volume manufacturing techniques Motorola used to getting 88 Iridium satellites in orbit in just over two years. (Though the Iridium service filed for bankruptcy protection in August, the satellite system is live.)
Molnau said that radical changes had to be made in every aspect of satellite design, including building separate facilities for front-end and payload manufacturing and for final systems integration. Hardware modules were based almost exclusively on surface-mount technology, with more than 60 BGAs employed, including several for the PowerPC 603 and 604 CPUs. In final assembly, the satellites were kept horizontal and rolled when subassemblies were to be installed via automotive-style assembly lines.
Many in the audience assumed that such methods would only make sense if 20 to 25 satellites were being built. But Molnau said the price break comes after five or six birds of the same model are manufactured.