HILLSBORO, Ore.--Endeavor Intertech Corp. here today announced an agreement with Synopsys Inc. to develop hardware/software co-verification models for a range of processor core architectures, starting with IBM Corp.'s PowerPC 405.
"Our goal is to continue to raise the industry bar for accuracy and performance in hardware/software co-verification," explained Geoffrey Bunza, vice president of the Large Systems Technology Group at Synopsys. "We believe that it is necessary -- and Endeavor Intertech has demonstrated that it is possible -- to produce software models that are cycle-accurate."
Under the agreement, Synopsys of Mountain View, Calif., will distribute models, developed by Endeavor Intertech, as part of its hardware/software co-verification offering in the Eaglei product line. Endeavor Intertech will integrate instruction set simulator models, bus function models, and test suites into the Synopsys Eaglei series.
According to Endeavor Intertech, the project is intended to overcome the shortcomings of today's standard models for co-verification, which are often poor representations of processor core functions. The Hillsboro company noted that co-verification models are supposed to mimic hardware functionality cycle-by-cycle and pin-by-pin, but creating that capability is often too time consuming or complex for modelers.
To address that challenge, Endeavor Intertech said it has created a simulation framework that accelerates the process of modeling. The inclusion of those co-verification models in the Synopsys Eaglei environment is expected to reduce design time and improve product quality before system-on-chip prototypes are built.
"We believe simulation model validation is a crucial concern for co-verification," said Dan Budge, vice president and chief technical officer of Endeavor Intertech. "We test our simulators against the original test vectors from the processor designers whenever possible, in addition to using their functional and timing tests. This insures that our simulators work exactly like the real thing, even to the level of pipeline bus cycles and multiple parallel busses."
Models for IBM's PowerPC 405 core are scheduled to become available by the end of December.