LEUVEN, Belgium -- Target Compiler Technologies NV, which has been developing high-level DSP hardware-software co-design tools since 1996, has persuaded STMicroelectronics to design its next generation ADSL chip using Chess/Checkers tool suite.
Since its spin-off from IMEC, the nearby microelectronics research center, Target has supplied EDA tools for designing, instantiating and programming IP cores and a complementary processor description language nML.
The Chess/Checkers tool suite has now been used to tape-out STMicroelectronics latest ADSL customer premises equipment chip, Target said.
Two blocks of circuitry, both involved in iterative algorithms and high data throughput operations, were on a critical path to achieving 20-Mbit/s data rates, doubling the data transmission rate of standard ADSL-1 and ADSL-2 products, Target said.
The Target tools include a retargetable compiler, called Chess C, which compiles C language application code to an application-specific processor developed from the application code.
The result is superior performance and computational efficiency compared to other software-programmable approaches, the company said. The use of the tools allows the performance of a hardwired ASIC but maintains flexibility through C programmability, the company claimed.
"Target Compiler Technologies provided a solution that not only gave us the flexibility we required, but did not jeopardize the performance and die size characteristics that our customers demand," said Leon Cloetens, vice president of the telecom group and general manager of the access products division of STMicroelectronics, in a statement.
"By designing their DSP cores using our tools, ST was able to utilize the characteristics of the algorithm to achieve an optimal match with their dedicated processor architecture," said Tony Picard, sales and marketing manager at Target, in the same statement. "In addition, ST has used the retargetable tool-suite to make dramatic changes in the algorithm and functionality very late in the design cycle, added Picard. "This allows full management of the embedded processors with a very dedicated ASIC-like data path. Once the optimal match between the architecture and the software applications was found, ST was able to automatically produce synthesizable RTL code."
In addition the Chess/Checkers tool-set supported the use of other EDA tools. It was possible to use Chess C with System C code to support co-simulation and hardware validation.
STMicroelectronics is in the process of designing several more programmable ASICs using the Target tools, Target said.