Prior to joining foundry chipmaker Taiwan Semiconductor Manufacturing Co. Ltd. as its chief technology officer in 2001, Calvin Chenming Hu served as a professor of electrical engineering and computer science at University of California Berkeley. He was also founding chairman of Celestry Design Technologies, an IC design software company that was acquired by Cadence Design Systems in 2003.
SBN: You have spoken enthusiastically about the use of 193-nanometer wavelength immersion lithography to get TSMC down to the 45-nm manufacturing process technology node, and dry and wet 157-nm lithography having the potential to take the industry down as far as 15-nm critical dimensions. If the incremental development of lithography is looking good, what are the next challenges limiting manufacturing?
Hu: Traditionally lithography has been the most difficult element in manufacturing. So with immersion lithography gaining support it's making things a lot better. I was at a recent ITRS International Technology Roadmap on Semiconductors meeting and saw someone present a slide with a red brick wall marking a roadblock on the development path. And jumping over the wall was a horse marked 'immersion'.
After lithography, well, there are enough problems to go around, but the next big one is power density.
The only way we really know how to reduce active power is to reduce the voltage. We also need to reduce standby power. But transistors don't work so well at reduced voltage. It's a matter of maintaining performance at low voltage.
That shows why gate leakage current is important. We've been trying to find high-k materials to replace silicon dioxide but it has been more difficult than expected. The results are delayed.
SBN: What can be done about that?
Hu: Either we have a crash program to work it a materials solution out or we substitute novel device structures such as FinFETs.
That's partly what I meant about using three-dimensional devices (referring to his comments during a panel discussion on getting to the 65-nm process technology node, held during Semicon West).
SBN: What about using germanium-on-insulator or other substrates engineered at the wafer-level for higher electron mobility? Will SOI and its derivatives become standard in the industry?
Hu: Yes, at 65-nm and beyond we certainly see strained-silicon coming in.
SBN: and Germanium-on-insulator?
Hu: Yes, well high-mobility materials in general. It all comes back to the power consumption. If you can get increased mobility you can achieve increased performance with fewer electrons.
SBN: But of course the use of pure germanium as a semiconductor material was abandoned forty years ago because it was 'difficult' to work with in the wafer fab.
Hu: Yes, the small band-gap makes the leakage current larger, but we've reached a threshold of pain over leakage current. And you couldn't use silicon dioxide with it. Some people think the high-k materials might work better on germanium.
SBN: But modifications in electron mobility, in reduced leakage currents can't offset the power consumption if miniaturization scales to billions of transistors on a chip. How do we get the heat out?
Hu: That is the question.
Maybe circuit techniques, circuit-level power management. We will have to be able to turn off circuit blocks on a fine-grained basis. Or rather, turn circuit blocks 'on' only when they are needed.
There could also be algorithm changes. Parallel processing is a good way to trade silicon die area for power consumption. Two blocks doing the same task as one block at half the clock frequency and at reduced voltage can save power.
Then there is the application of lots of functions on chip but where each is called infrequently. I see it like the software on my PC. There are hundreds of programs on there but I spend most of my time using just a few of them.
Also we can substitute memory for processing power and communications bandwidth, and that can really save power. So you build lots of memory on-chip and use it to cache as much data as possible, and then you don't spend time and energy processing data or fetching it.
SBN: But what about radiation problems effecting the scaling of SRAM? Can single-event upset be got around on-chip or in packaging?
Hu: It will be done by error correction.
SBN: How quickly do you think these tri-gate, OmegaFET and other wrap-around gate devices will start getting deployed?
Hu: FinFETs: really they're all different types of the same thing. I think it is going to be used, but not wholesale. There won't be a chip where you look in and every transistor is a FinFET. No, it will be used selectively where the performance requires it. I think it could come as early as the 65-nm node.
SBN: And what about the choice of next-generation memory; magnetic RAM versus ferroelectric RAM verus phase-change memory. Does TSMC have a technology it is favoring?
Hu: The consequence of that choice is so large we cannot afford to miss out. We are not the leader in any of the technologies. But we do have programs on MRAM and on phase-change memory.
SBN: Do you see an eventual transition from the scaling of FinFET transistors to single-electron and quantum effect devices?
Hu: I don't think it will be a smooth transition. It's going to be a quantum jump. I expect incrementalism based on the development of CMOS to take us a lot further than most people think. But only time can tell.