CHARLOTTE, N.C. -- Engineers from three semiconductor companies detailed their experience using novel design-for-test techniques to speed chip testing during volume manufacturing at the International Test Conference here.
Presenters from Infineon Technologies A.G., Intel Corp. and Texas Instruments Inc. made their case for each.
The Intel approach is a Hybrid DFT (H-DFT) architecture for low-cost, high-quality structural testing. Intel made a strategic decision several years ago to gradually shift from traditional functional testing to structural testing. The key motivation for the shift was minimizing the need for high-speed functional testers and manual test writing.
The Intel authors said structural test, however, is facing the challenge of mounting test-data volume and test time due to an exponential growth in the number of transistors per die. Another issue is the need to apply not only stuck-at test patterns but also delay test patterns such as transition fault patterns.
Huge pattern size not only increases test time but also requires additional tester memory on structural testers with increasing capital cost. Therefore, the authors said it is highly desirable to develop design-for-testability techniques to significantly reduce tester memory requirements and test time.
Authors from Texas Instruments Ltd. in Northampton, UK described a circular BIST testing methodology for digital logic within a high-speed serializer/deserializer. High-speed serdes are traditionally tested using functional BIST. The authors described an improved BIST technology for testing the digital portion of a serdes using circular BIST.
A serdes contains both analog and digital CMOS circuits running at data rates up to 3.2 Gbits/s and clock frequencies up to 1.6 GHz. Serdes are also highly integrated with up to 128 receiver/transmitter pairs found on some designs.
Manufacturing testing of such designs is performed with digital testers whose capacity falls short of the required data rates by a factor or two or more, the TI engineers said. This can be overcome by an external loopback test " connecting receiver and transmitter pairs together externally on the test fixture and running short functional at-speed data streams from the transmitter to the receiver.
Using circular BIST the TI engineers reported successful testing of the digital logic of the high-speed serdes macro at speed with a resultant fault coverage of 93 percent and a gate overhead of 7 percent.
Meanwhile, Infineon has adopted an embedded deterministic test (EDT) technology in its design flow as a way to reduce the cost of manufacturing test without compromising quality. Infinion said experience has demonstrated that since EDT is based on the standard scan/ATPG methodology and does not require modification of the design, it can be successfully adopted with little effort, no performance impact and minimal area overhead.
EDT technology is based on two complementary parts: hardware that is embedded on chip and a new deterministic ATPG software algorithm that generates highly compressed patterns that utilize the embedded hardware. The EDT hardware is inserted along the scan paths and does not require any modifications to the functional logic. It consists of a continuous-flow decompressor that maps the few external scan channels into a large number of internal scan chains, and a compactor that compacts the large number of internal scan chains into a few external scan channels.