San Jose, Calif. -- PDF Solutions Inc., a provider of yield optimization solutions for fabs and foundries, is expanding into EDA with a tool that claims to improve designs for optimum yield during the physical-synthesis step in the digital IC design process.
The new pDfx tool encapsulates the yield improvement process knowledge the San Jose company has gained through its service engagements with chip makers, said vice president of marketing Michael Buehler-Garcia.
"Before 130 nanometer, the 'D' in DFM design-for-manufacturing was silent. It was the fab guys' problem," said Buehler-Garcia. "At 130 nm the lines are blurring between design and manufacturing." Obtaining predictable yields at 130 nm requires an intimate knowledge of fab processes, he said.
The pDfx tool contains two DFM software technologies and a process kit with fab and process-specific models and intellectual property (IP). It targets standard-cell processes, but memory and analog are on the road map.
Used after IC floor planning, the tool directs physical synthesis to create yield-optimized designs. It runs with Cadence Design Systems Inc.'s RTL Compiler, Synopsys Inc.'s Galaxy platform and Magma Design Automation Inc.'s BlastFusion platform, Buehler-Garcia said.
Riko Radojcic, director of design portfolio business development at PDF Solutions, explained the process. After designers create a floor plan that meets power and timing requirements, they will import it into pDfx in the .db format. The tool's estimator technology examines the design and its optimizer technology prompts users to specify yield requirements. "The tool lets you pick 'care abouts' for your specific design," said Buehler-Garcia.