AUSTIN, Texas -- Aided by a key contribution from a Russian scientist who died young, Motorola Inc. is claiming to have essentially solved one of the major challenges facing magnetoresistive memories, with technology it has incorporated in 4-Mbit MRAM samples shipping now to select customers.
That puts Motorola's Semiconductor Products Sector one quarter ahead of its announced schedule for MRAM sampling. The company expects to begin pilot production of discrete MRAMs at its Chandler, Ariz., fab by late 2004, and then move on to its primary goal: embedding MRAM arrays in logic products where fast programming times, nearly unlimited endurance and nonvolatility are important.
A microcontroller that now has separate SRAM and flash arrays, for example, could be served by an embedded MRAM array partitioned according to the needs of the system designer, said Rick Sivan, director of Motorola's embedded-memory center here. "We haven't seen any red flags that might stop the progress of MRAM," said Sivan.
One issue hobbling MRAM technology has been the tendency of a neighboring bit to be disturbed, or "flipped," when a nearby bit was being programmed by changing the magnetic state of the cell. Leonid Savtchenko, a Russian scientist who worked at Motorola's MRAM development center, is cited as the key inventor on U.S. patent 6,545,906, issued to Motorola last April, which describes a "toggling" solution to the bit-disturb problem. Motorola is likely to license the toggling patent to other companies developing MRAM, in an effort to promote wider use of the technology.
Savtchenko died of a brain aneurysm on June 10, 2001, at the age of 35. A co-worker, Brad Engel, said Savtchenko was the magnetics theoretician in the Motorola MRAM group, which he joined in 2000 after moving to the United States from Russia with his wife and young daughter. He received his doctorate in physics from Moscow State University in 1997.
"He was an extremely talented individual with a superb mastery of physics and simulation coding. He was the originator of our unique writing mode, which we now refer to as 'Savtchenko Switching,' " Engel said.
"He died before he got to see the fruits of his work," said Saied Tehrani, director of the MRAM development group in Phoenix.
The toggling approach will be more fully described in a paper, "dedicated to the memory of Leonid Savtchenko," that Motorola engineers are due to present at the International Electron Devices Meeting, set for December 8 to 10 in Washington, D.C.
In a conventional MRAM, a bit is represented by a magnetic tunnel junction (MTJ), which includes a pinned magnetic layer, a tunnel barrier and a free magnetic layer. The free layer is switched from one magnetic polarization, or direction, to another by using two metal connections, one of which can carry current in bipolar mode -- that is, current can flow in either direction.
Rather than flipping the bit with the bipolar current, the toggling approach uses two overlapping pulses, Tehrani explained. The first pulse rotates the angle of the magnetic field and the second rotates it slightly more, toggling the direction of the magnetic field.
Also, the approach requires that every write must have a prior read sequence to determine which bits need to be toggled. That read sequence cuts the number of bits that must be toggled approximately in half, reducing the amount of power needed to program the array, Tehrani said.
"Through the read sequence, the chip knows that if the direction of polarity is correct for a certain bit, it leaves it alone. If the direction needs to be changed, it turns on" and reverses the polarization of that bit, Tehrani said.
The toggling invention is particularly important as MRAMs scale to 90 nanometers and beyond, because the energy required to inadvertently flip a neighboring bit decreases as the MTJ is scaled.
Even though some other companies have struggled to reduce the cell size of their MRAM prototypes, Sivan said that for an 0.18-micron logic process, the MRAM cell size is about 1 square micron-roughly the same as embedded DRAM and flash cells, and about one-third the SRAM cell size at the same design rules. Motorola plans to jump to 90-nm design rules later, and early 90-nm prototype cells have a cell size of 0.3 square micron, he added.
Sivan said the programming time for MRAM is 1,000 times faster than for embedded flash and roughly similar to embedded DRAM.
Motorola's main effort is to develop a form of embedded MRAM that can be used with microcontrollers and other logic products. It also has a small team investigating a form of MRAM that resembles a serial flash device, in that a series of MTJ cells are controlled by the word and bit lines, rather than having one transistor matched with each magnetic tunnel junction. This "zero T" or "crosspoint" approach involves stacking a series of MTJs vertically, perhaps six to eight high.
"The zero T is not our main thrust, but there are potential customers, certain applications, that require massive amounts of memory," Sivan said. "At Motorola, our first target is performance, and we think the cell size and power consumption that we have now are manageable for the applications we have in mind."
Fred Zieber, president of Pathfinder Research (San Jose, California), said he sees MRAM as a form of flash replacement. "It appears that Motorola has solved some problems that others haven't at this stage," said Zieber, who counts eight or more companies working on some form of MRAM technology. He called the toggling approach "a big step along the way toward making MRAM a commercial memory. Before that, you basically had an open-flux system, and when one bit was switched, it would affect the neighbor."
Motorola's announcement comes four months after an IBM-Infineon joint-development effort announced 128-kbit MRAM prototype arrays, also using 0.18-micron rules.
Zieber said MRAM appears to be making faster progress than the so-called Ovonic memory types, which he said are facing materials issues, or ferroelectric RAMs, which may be difficult to scale. "MRAM could be the universal memory," Zieber said. "It is nonvolatile, it is fast, it is rad-hard for space applications and it uses silicon technology. On the flip side, MRAM is chasing stuff, like DRAMs and flash, that from a cost point of view are moving down the learning curve at 30 percent a year -- though I do believe that MRAM is not inherently costly."
Tehrani said that after eight years of working on MRAM development at Motorola, "the most important thing is that we are sampling. That is a real milestone that we are very happy about."
Motorola is not discussing its own plans for MRAM usage, though in the past the company has identified automotive controllers, cell phones and MCUs as obvious targets. Last week, the company said that security, gaming and computer-peripheral customers were interested. Some customers want a cache memory that needs no battery backup, as SRAM cache requires.
"The people that are interested in discrete MRAM need the fast programming and unlimited endurance," Tehrani said. "These give them a system advantage, and so we may go into the market with these discrete parts that we are sampling now. But our primary, long-term interest is in embedded MRAM."