Santa Cruz, Calif. -- Armed with new technologies supporting design-for-verification, Mentor Graphics Corp. this week said it will roll out its Scalable Verification platform. With it, Mentor claims to be first with full Verilog 2001 support, transaction-level testbench generation for emulation and an HDL link to Matlab and Simulink from The Mathworks.
"We now have scalability and performance where we didn't have that before," said Robert Hum, vice president and general manager of Mentor's design, verification and test division. Mentor verification users, he noted, can now work at a number of abstraction levels, starting with algorithmic design in Matlab and working down to Seamless hardware/software co-verification, VStation emulation and ModelSim HDL simulation.
ModelSim version 5.8, which is due to ship in November, adds Mentor's first support for Accellera's SystemVerilog 3.1 standard. This support encompasses what Hum called "productivity features," including literals, user-defined types, enumerated data types, structures and unions, dynamic arrays, port connections and interfaces.
ModelSim 5.8 also claims full support for SystemVerilog's predecessor, Verilog 2001. Many Verilog users have noted that vendor implementation of this IEEE standard has been spotty. "To our knowledge this is the first time Verilog 2001 has been completely supported," said Hum.
The tool does not yet include SystemVerilog 3.1 assertions, but those will come next year, Hum said. Meanwhile, ModelSim 5.8 adds a built-in "assertion engine" that works with Accellera's Property Specification Language (PSL) version 1.0. This engine monitors assertions to see if they fire or don't fire, and reports back to the designer through a graphical user interface.
"PSL and SystemVerilog 3.1 semantics are identical, but the syntax is a little different," Hum noted. "We chose to compile PSL syntax. We will compile SystemVerilog 3.1, but it's not out yet."
Hum described another component of the platform, VStation Pro, as the "next generation" of the VStation product line acquired from Ikos Systems. The machine, he said, supports capacities ranging up to 120 million system gates. But the main new feature is its support for VStation TBX, a new product that makes transaction-level testbenches available for emulation.
"TBX makes testbenches scalable," Hum said, adding that the technology "can give you an acceleration of 100 to 1,000 times over anyone else's testbench technology. And it works with HDLs or C, not just with a Mentor language."
TBX compiles behavioral code into testbenches that run on the VStation Pro. Instead of sending pin-level signals, Hum noted, it sends transaction-level data structures. "Usually your speed is determined by the link between the workstation and the emulator," he said. "If you insert TBX, the traffic on that link drops and the emulator spends less time waiting for the workstation."
Finally, Link for ModelSim-a product that will be sold by The Mathworks-links Matlab and Simulink with ModelSim. The product lets designers create a software testbench of HDL code in Matlab or Simulink, which are widely used for DSP algorithm development and simulation, and verify the code against its original specification. It thus allows Mathworks users to incorporate HDL code into their simulations.
Link for ModelSim can also be used with Xilinx's System Generator and Altera's DSP Builder.
ModelSim 5.8 pricing starts at $4,495. VStation Pro, available now, starts at $300,000. VStation TBX, available now, is priced based on capacity. Link for ModelSim, which will be available in November from The Mathworks, starts at $2,000.