LONDON -- Engineers from foundry chipmaker Taiwan Semiconductor Manufacturing Co. Ltd. have developed a 45-nanometer planar silicon-on-insulator manufacturing process that can be made using 0.85 numerical aperture 193-nm wavelength lithography.
A paper on the manufacturing process is expected to be one of the highlights of the VLSI Technology and Circuits Symposia due to take place June 15 to 19 in Honolulu, Hawaii.
According to a prcis of the paper, all the critical levels can be patterned with contemporary 193-nm lithography as long as resolution enhancement techniques are used, including optical proximity correction, and optimised illumination. Apparently, the paper demonstrates planar SOI's "relative ease of scaling" compared with bulk silicon. The process requires no major changes from 65-nm SOI requiring only a reduced gate spacer and SOI body thickness, according to abstracted details.
The manufacturing process is discussed in the context of a six-transistor SRAM with a cell size of 0.296 square microns.
It's planar nature means that finFET type devices are not required. The use of immersion lithography is not discussed, suggesting that the manufacturing process is dry and could benefit by the addition of immersion for either an improved depth of field or, with higher NA lenses, for improved resolution.
The process includes strained engineering for optimised transistor drive current and 30-nm physical gate lengths. The paper reports device operation characterized at both 0.85-volts and 1.0-volts with the SRAM operating down to 0.60-V.