LONDON -- Mentor Graphics Corp. is set to launch a C-to-V synthesis tool Monday (May 31) but claimed it has enjoyed success with C synthesis software with a number of blue chip customers for several years. Until now the company had been reluctant to come out with a product in what had been a confused and difficult market place.
The company's technology takes an untimed C++ software description of a function and allows automated error-free RTL creation in either VHDL or Verilog, the company said. It can do this up to 20 times faster than traditional manual methods, it claimed.
"This uses untimed C++ code, not System C which adds timing information," said Thomas Bollaert, European product specialist for Mentor. "The design starts out functional, not architectural but it explores micro-architecture and allows 'what if' analysis."
After coming under pressure from existing customers to announce their technology as a product, Mentor decided to call it Catapult C and take it to a broader market, according to Wally Rhines, Mentor president and chief executive officer.
The Catapult C synthesis tool targets designers developing ASICs or FPGAs for compute-intensive applications such as wireless communications, satellite communication and video/image processing.
Mentor claimed that despite the existence of multiple alternative languages aimed at hardware synthesis untimed C++ source is still that most commonly used by system designers to describe their systems.
The Catapult C synthesis tool is the only EDA product to synthesize a C++ source where both the core algorithm and the interface are untimed, Mentor said. The tool creates an RTL description, which can then be synthesized to a gate-level description using standard RTL synthesis products.
It is expected that dot-lib files would be used from particular implementation technology to allow performance versus area trade-offs to be made at the high level of abstraction. The Catapult C synthesis tool has a Library Builder routine to collect this detailed characterization data from downstream RTL synthesis tools.
Catapult C is not aimed at broad-brush architectural comparisons but rather is used after partition to synthesize particular logic blocks. Support is given for the selection of word widths and determining a fixed-point interpretation from floating point math. However, it cannot automatically select or choose between micro-architectures.
"It still requires engineering skills to converge on the right architecture," said Bollaert.
However, one reason for the existence of a multitude of alternative high-level languages is the accepted wisdom that sequential C with its abstract data types could not be synthesized to hardware description languages without modification.
"The original intent of those languages was simulation not synthesis," said Bollaert. "In our case timing is added via a constraints file, without modifying the code."
The biggest argument in favor of Catapult C is the number of high-level supporters Mentor was able to mobilize in support of the product's 'launch' and the backlog of successful designs.
Bollaert said Mentor already has 20 customers across Europe and North America and C synthesis experience on ten tape-outs.
STMicroelectronics NV, a supporter of CoWare NV in the past, has been using the Catapult technology since August 2001.
"Using Mentor's Catapult C synthesis we were able to create a Reed-Solomon decoder with results equal to the best published paper in a matter of days," said Henri Michel, Shiva team manager at STMicroelectronics central R&D.
"Our ability to achieve a 31 percent reduction in gate count, which correlates closely to silicon real estate and power consumption speaks for itself," said Peter Nord, project leader EDA and methodology co-ordination, Ericsson Mobile Phones.
Other users include Alcatel Espace and Siemens ICN.
Rhines said senior management at Mentor had been adamant that there had to be strong demand from beta customers for the technology before it would commit. "Those beta customers are always concerned that until the EDA company formally launches the product there is a risk it might get dropped or support may not be maintained."
Mentor has now decided to take the technology out to a broader market. The Catapult C synthesis tool environment is available immediately on one-year term and perpetual licensees and ranges in price from $89,000 to $275,000 depending on the length of license and FPGA or ASIC target.
Three-year term licensees are thought to be available as well.