TOKYO -- Toshiba Corp. has developed technologies that it says will extend the life of bulk CMOS as far as the 22-nanometer technology node, which won't reach production until 2016, according to the timetable set out in the 2003 edition of the International Technology Roadmap for Semiconductors (ITRS).
The announcement thus appears to contradict the ITRS prediction that "the end of planar bulk CMOS is becoming visible."
Toshiba engineers have designed a bulk CMOS transistor with 10-nm gate lengths, which corresponds to the hp22 technology node outlined in the ITRS. Toshiba said that the simulated performance of the transistor almost satisfies the requirements of the hp22 node. "For volume production, especially the conformity with embedded memories, planar bulk CMOS devices are desirable," said Nobuaki Yasutake of the Advanced CMOS Technology Department at the Toshiba SoC Research and Development Center.
Bulk CMOS has been the industry's production technology of choice for almost two decades for integrating such circuits as analog, RF and memory on a system-on-chip. But its shortcomings are becoming more troublesome as line widths decrease.
Transistors with less than 10-nm gate lengths have already been reported. But the performance of those transistors, as represented by the ratio of drive current (Ion) to off-current (Ioff), did not reach the level called for by ITRS 2003.
That latest edition of the industry road map set target specifications for devices for low operating power at the 22-nm technology node at 0.03 microampere/micron for Ioff and at 920 A/micron for Ion. Thus the ratio of Ion to Ioff " a larger figure means better transistor performance " was 30,667.
Toshiba said its transistor simulation had an Ion of 790 A/micron and an Ioff of 0.01 A/micron, for a ratio of 79,000, exceeding ITRS' 20003 performance target.
The key technologies that Toshiba engineers introduced for the transistor were an elevated source/drain extension structure, a fully silicided metal gate and the oxynitride (SiON) gate dielectrics, which enable a thin layer with low leakage. Each of the technologies was optimized to realize the desired performance.
An NMOS transistor produced by Toshiba had a drive current of 730 A/micron and an off-current of 2.2 A/micron, which did not satisfy the ITRS requirements. But the combination created a transistor with the performance of 79,000. In the past, Yasutake said, "bulk CMOS devices could be scaled down, but the performance deteriorated. We now have prospects for improving performance." The drive current called for by the ITRS is an even smaller target, however, so the research team intends to work on improving the transistor performance, including the drive current.