SAN JOSE, Calif. During the Microprocessor Forum here on Tuesday (Oct. 5), Advanced Micro Devices Inc. disclosed some of the first details of its dual-core microprocessor design.
AMD (Sunnyvale, Calif.) has previously announced plans to roll out a dual-core design, built around its x86-based, 64-bit Opteron line. "Multi-core is the next big step in x86 technology," said Kevin McGrath, a Fellow for AMD's California Processor Division, during a presentation at the event.
The company's dual-core processor is a 205-million transistor chip, based on a 90-nm process and silicon-on-insulator (SOI) technology. The device is approximately the same die size as a single-core, 130-nm Opteron processor, McGrath said. The 940-socket compatible chip is said to have a 95-Watt power envelope, he said.
AMD plans to integrate two Opteron processor cores on a single die, based on a symmetric multiprocessing programming (SMP) model. Each core consists of 1-MB of L2 cache.
AMD directly connects the processor cores to the peripherals and core logic, which the company calls the "AMD Direct Connect Architecture." The architecture reduces bottlenecks and latency, McGrath said.
The cores work in conjunction with a combination system request interface (SRI) and crossbar switch, which, in turn, are linked to a shared Northbridge device. This device consists of three HyperTransport technology links and a dual-channel, 128- bit DDR interface.
The processor design also consists of hardware pre-fetch enhancements. It also has 10 new SSE3 instructions. It also includes four write combing buffers and power savings features in the C1/C2/C3 states.
"The dual-core part is in our labs and will be sampling soon," McGrath said. The company expects to introduce dual-core chips for the one- to eight-socket server and workstation market in mid-2005. Dual-core processors for the client market are expected to follow beginning in the second half of 2005, according to a presentation by the company.