The following article was contributed by Tom Lee, founder and director of advanced development at Matrix Semiconductor Inc., a developer of three-dimensional integrated circuits. Lee is also a professor of electrical engineering at Stanford University.
Various concepts for three-dimensional (3D) electronics have been explored for many years. Interest in designing 3D semiconductor products has been particularly high in the last decade. In seeking to advance the state of the art, the semiconductor industry has discovered that:
1) A serious examination of the possibilities beyond a wafer's 2D plane has been long overdue.
2) Leveraging the third dimension in product design and manufacturing is practical and achievable.
After a long gestation in which many problems were overcome, 3D electronics is now a proven concept that is shipping in volume. However, the absence of a uniformly accepted definition has created a new problem: confusion as to what the term "3D electronics" really means. The term's recently acquired cachet has also encouraged some to apply it to rather ordinary technologies, further compounding the confusion.
Matrix Semiconductor Inc. (Santa Clara, Calif.) believes that it has achieved a unique answer by developing 3D integrated circuits, that is, multiple layers of semiconductor devices within a single (or "monolithic") chip. In contrast, other companies employ techniques that bond multiple dice together, almost like a multi-chip package connected at the wafer level. Still others call optimizations of single-layer designs "3D" because the layer of devices incorporates 3D shapes for better packing density.
Comparing all of the approaches that claim a 3D nature shows that, not only are some approaches more "3D" than others, but that each approach seeks to solve very different problems from cost to physical size to performance. These approaches to 3D electronics are so different, in fact, that it is difficult to evaluate and compare them fairly.
Arguably, they actually fall into very different category types and not all "3D" technologies are the same or even deliver similar benefits.
What is 3D?
One common goal of 3D electronics is a reduction in size. Dynamic RAMs, for example, have long used cell capacitors built out of deep trenches in order to increase capacitance per unit area. The performance demands of digital logic have driven the development of multiple levels of metal to reduce interconnect delays. Twenty years ago, products with more than two layers of metal were rare; today, interconnect stacks with a half-dozen or more metal layers are common.
These early exploitations of the third dimension have all produced an important reduction in die area, but are more properly regarded as extensions of the planar paradigm, because no semiconductor devices are fabricated outside of the substrate. This limitation bounds the size and cost reductions that can be achieved with those techniques.
Package- or chip-stacking methods provide more dramatic size reductions. For example, prefabricated individual chips may be encapsulated within a small carrier, and then assembled into a module. Alternatively, individual dice can be stacked and interconnected, and then encapsulated in a package. These packaging technologies enable products with much smaller form factors, and offer the added advantage of not requiring any fundamental changes to integrated circuit manufacturing technology.
Furthermore, the individual elements could be integrated circuits built in a mix of technologies, enabling new functionality, such as combinations of optical components or sensors with conventional electronics. However, products made with these "back-end" 3D techniques offer little or no reduction in cost.
Indeed, yield limitations arising from the "known good die" problem can actually cause costs to rise. Back-end 3D technologies are attractive where cost is relatively unimportant, but size and performance are paramount.
Monolithic 3D integration is unique in that it enables both size and cost reductions. This "front-end" approach to 3D electronics extends the planar paradigm fully into the third dimension, by fabricating semiconductor devices above the substrate. Because die cost is, to first order, a function of area, the ability to build more devices per unit area enables a cost reduction at the same time size is reduced. Monolithic 3D circuits are well matched to markets that value low cost and small form factors.
Finally, one could imagine combining front-end and back-end 3D approaches. Although no one is currently shipping products of this type, this example serves to underscore the fact that 3D electronics is here, and available in a number of incarnations, distinguished by whether the 3D technology is deployed at the back-end or front-end.