BURLINGTON, Mass.--April 28, 2003--Xelerated, a fabless semiconductor company on the verge of revolutionizing the market for high-performance network processors, announced the availability of its X10q-e Network Processor. The X10q-e enables system vendors to build cost-effective, flexible, wirespeed solutions for the enterprise backbone and metro Ethernet markets. The X10q reference design system running at 40 Gbits/s was demonstrated at NetWorld+Interop 2003 in Las Vegas April 29May 1, 2003.
Low-cost solutions for gigabit connectivity to the edge of the enterprise network are now available, and this is driving the need for cost-effective, multi-port GbE and 10 GbE line-card solutions for the enterprise backbone and metropolitan area networks. Merchant silicon has played a leading role in driving down the cost of edge connectivity, but enterprise backbone and metropolitan area networks require a combination of wirespeed performance and flexibility not offered by standard, off-the-shelf ASICs. Xelerated's new patent-pending data-flow architecture allows the X10q-e to meet these requirements while maintaining the strict cost and power requirements of the enterprise.
"With the recent set of new product announcements, it is clear that the multi-gigabit Ethernet wave is starting," says Michael Howard, principal analyst at Infonetics Research Inc. "The availability of innovative technology like the X10q-e will further fuel that wave, enabling more cost-effective solutions for multi-gigabit enterprise backbone and metro Ethernet systems."
Until now, programmable architectures have been burdened either by low performance or by high power dissipation, making them unsuitable for enterprise backbone equipment, leaving expensive custom ASICs as the only development choice. The X10q-e offers a unique combination of flexibility and efficiency that is particularly well-suited for this market.
"The speed with which Xelerated has moved from the SONET to the Ethernet market is a testament to the flexibility of their architecture," says Linley Gwennap, principal analyst at the Linley Group. "And at less than 6.5 W per 40 Gbits/s, they have set a new mark for network-processor efficiency that traditional programmable architectures will be hard-pressed to match."
"The lower packet rates of Ethernet relative to SONET have allowed us to scale back processing power and improve bandwidth efficiency relative to our SONET offeringswhile still maintaining 40 Gbits/s wirespeed performance," says Gary Lidington, VP of marketing at Xelerated. "The benefit we bring to our customers is that we have helped to level the playing field. Now they can build cost-competitive, yet differentiated products for the enterprisewithout spending tens of millions of dollars to develop all their own ASICs."
Xelerated's X10q range now includes two new offerings: the X10q-e and the X10q-m, each priced based on their packet-processing rate. The original 40 Gbits/s SONET offering has been renamed the X10q-w. The original 20 and 10 Gbits/s SONET offerings will be phased out over time.
|Xelerator X10q NPUs (4*SPI4.2)
||Max. Packet Rate
|X10q-e High-Density Ethernet (n*1GbE and n*10GbE)
|X10q-m High-Functionality Ethernet/SONET
|X10q-w High-Density SONET
As a part of these new offerings, the X10 will also support a new advanced search-capability solution that leverages standard DRAM technology. This will reduce the cost of supporting large tables without stealing valuable processing cycles from the processor cores.
First silicon for the X10 was received in early January, and customer demonstrations have been taking place since early February. "The response from our customer base has been very positive, and we are now working in a number of customer projects," says Johan Börje, CEO of Xelerated.
Enabled by the availability of 0.13 µm process technology, the X10 architecture is the first known commercial implementation of a data-flow processor. This unique architecture is optimized for the efficient movement of data, eliminating the need for complex inter-processor interconnects as well as redundant data and instruction storage. This allows 200 data flow processors and ten I/O processors to fit on a single, low-cost chip, providing unparalleled cost/performance. The 200 data-flow processors are organized in a synchronous pipeline with each processor executing a single instruction. This makes them appear to the programmer as a single 80 BOPs processor with a fully deterministic execution time. The benefit over conventional multi-RISC based architectures is a much simpler programming model and guaranteed wirespeed performance.
"We are very impressed with the X10q-e," says John G. Metz of Metz International in Harvard, Mass. "Xelerated has taken racebred technology and made it practical enough for use on the streetno one we know can match their level of programmability, performance, power, and price."
Xelerated is a fabless semiconductor company developing high-performance network-processor solutions for manufacturers of Enterprise, SAN, MAN, and WAN networking equipment. Xelerated's product is the world's first programmable network processor with ASIC efficiency. The outstanding efficiency translates into the highest packet rate, the highest port density, the lowest cost per port, and the lowest power consumption per Gig on the market.
Xelerated has offices in Burlington, San Jose, and Stockholm.
Additional information about the company and its products is available at www.xelerated.com.