By David Lammers , EE Times
Though 90-nanometer designs are not expected to move into early commercial production until late this year, about a dozen papers at the 2003 VLSI Technology Symposium will target 65-nm design rules.
Full-blown 65-nm technology demonstrations are expected at the symposium-planned for June 10-12 in Kyoto, Japan-from NEC Corp.; a Motorola Inc.-Philips-STMicroelectronics process development team working in Crolles, France; and a Toshiba Corp.-Sony Corp. joint development effort (see www.vlsisymposium.org).
Other presentations will take a narrower focus, examining the high-dielectric-constant (high-k) gate oxides, lithography and interconnect technologies re-quired for 65-nm design rules.
An abstract of the Toshiba-Sony paper describes an embedded SRAM technology at 65-nm line widths that achieves a cell size of 0.56 square micron, the smallest yet reported, with roughly half the area taken up by 90-nm SRAM cells. Toshiba also will present related papers on argon fluoride lithography, which uses a 193-nm exposure wavelength, and on the optical proximity correction techniques used for the SRAM demonstration vehicle.
The Motorola-Philips-ST team will present its 65-nm CMOS integration strategy as well, describing a 0.69-square-micron cell size for the early SRAM demonstration vehicle. NEC employed a triple-gate-oxide approach to the 65-nm technology node, one that serves to reduce the average standby current to one-fifth that of a conventional device. The NEC presentation describes metrics for both high-performance and low-leakage transistors used in the 65-nm platform.
The companion Symposium on VLSI Circuits, which will run June 12-14 at the same venue in Kyoto, will offer several sessions on new memory technologies, including an IBM Corp.-Infineon Technologies paper that describes the companies' cooperatively de-veloped magnetoresistive RAM test device with a cell size of 1.4 square microns. Judging by early results, the team predicts a 5-nanosecond random-access time and a sub-5-ns write pulse for the single-transistor/single-magnetic-tunnel-junction (1T/1MTJ) approach.
Texas Instruments Inc., with development partners Ramtron International and Agilent Technologies, will detail a 64-Mbit ferroelectric memory that was first described in December at the International Electron Devices Meeting. With a cell size of 0.54 square micron, the TI FRAM has an access time of less than 30 ns.
Toshiba and Infineon also will discuss their 32-Mbit chain ferroelectric RAM, which uses an approach that is said to reduce the signal loss inherent in chain FRAMs.
Several sessions are dedicated to emerging memories. Papers by Intel Corp. and Samsung will discuss phase-change, or ovonic, memories as well as Sonos (silicon-oxide-nitride-oxide-silicon stack) flash circuits, which store charge in a nitride layer.
Beyond memory technology, the VLSI circuits meeting will present a potpourri of wireless, telecom, storage and clocking circuits. Engineers from Intel's laboratory in Hillsboro, Ore., will present several papers on clock-timing adjustment technology, including the clock generator used in the latest Itanium processor.
Sony will present a single-chip global positioning system solution that integrates radio-frequency and baseband functions and that sports a power budget of 57 milliwatts.
A research group from Nippon Telegraph and Telephone (NTT) will present a Bluetooth chip that can operate from a single battery cell, an arrangement useful for lightweight wireless applications such as headsets. Based on a low-power form of silicon-on-insulator CMOS, the transceiver dissipates 53 mW in receive mode and 33 mW in transmit mode.
NEC engineers will present a chip that supports the serial ATA standard for hard-disk drives. The device uses spread-spectrum techniques to avoid noise issues that are common in the PC environment, including a self-running phase interpolator to recover the clock and data signals.
Wai Lee, a TI engineer who is the spokesman for the VLSI circuits meeting, said the first-generation serial ATA standard now coming to market supports 800-Mbit/second data transfers. The NEC device supports the next-generation serial ATA spec of 3 Gbits/s.
"These storage devices are not that much different than chips used in the telecom field, except that the boards used in the personal-computer environment are not as high-quality as boards used in routers. So NEC has used very high-level chip technologies to minimize the noise generated in the personal-computer environment," said Lee.
Sanjeev Aggarwal of TI holds up a wafer of 64-Mbit FRAM memory devices-a topic at the Symposium on VLSI Circuits.
Several papers at this year's technology symposium look at the still-difficult task of integrating high-k gate insulators to keep leakage current under control. A Motorola paper looks at the shifts in threshold voltage that occur when insulators based on hafnium oxide and aluminum oxide are combined with the polysilicon gate electrodes. Motorola's paper presents new arguments about the basic physics involved in the shifts.
Silicon strain, SARS stress
Presentations from Taiwan Semiconductor Manufacturing Co. and from Selete, Japan's privately funded semiconductor research consortium, examine aspects of the 65-nm interconnect stack, including how to integrate porous insulators with k-values of around 2.2. And several papers examine the use of strained silicon at the channel-a topic that first gained widespread attention two years ago when IBM presented its initial strained-silicon work at the 2001 Symposium on VLSI Technology.
Lee said the organizing committee is hoping that, despite the concern over SARS and the persistence of the semiconductor industry downturn, the technology symposium will draw its typical attendance of 400 to 500 people and the circuits symposium will command its typical attendance of about 350.
The Osaka-Kyoto region is in the grips of a SARS-related scare because a visiting Taiwanese doctor was confirmed to be infected with SARS after returning home to Taiwan from a trip to Osaka. But TI's Lee noted there have been very few cases of severe acute respiratory syndrome in Japan.
"SARS puts some uncertainty into this year's attendance. We'll have to see how the attendance holds up from Taiwan and Hong Kong," he said.