18-Mbit DDR II And QDR II Pipes Start to Flow
For quite some time, we have heard about the benefits of the next-generation Double Data Rate (DDR) and Quad Data Rate (QDR) parts. Already, first-generation parts have made their way into networking and telecom applications as well as Storage Area Networking (SAN) and other applications that demand high-bandwidth memory architectures. A recent announcement from Cypress now indicates that there are 24 parts to play with.
Samples of the company's 18-Mbit QDR, QDR-II, DDR, and DDR-II SRAMs are now starting to flow, and are taking direct aim at reducing latency for high-speed switches, routers, servers, and storage applications.
Following the logical progression, the new parts double the densities of the 9-Mbit parts released last year, and are a precursor to the 36-Mbit parts planned for release next year. According to Cypress, 72-Mbit parts will also start to trickle out next year.
So if you were smart enough to route the extra address lines to your board design, you should be able to populate it with the new parts and double your memory density without a redesign. Likewise, when the 36-Mbit parts are available, you should be able to double the density yet again, and again with the 72-Mbit parts.
What makes this possible is the fact that the address expansion lines are not connected to the die internally. This is important. Some suppliers require you to connect these lines to ground to help dissipate heat. This means that you can't wire them to the upper order address lines directly, and so you need to use a jumper arrangement.
The new 18-Mbit devices clock up to 250 MHz and provide up to 36 Gbits/s of bandwidth. The datasheet shows a 300 MHz part, but it is not available yet. Key with DDR and QDR parts is their low latency. In this case it is 1.5 cycles and 1 cycle for the DDR/QDR II and DDR/QDR I respectively.
But note that if you are using QDR, you can't just put in a QDR II part. The QDR uses a 2.5 V core power supply with HSTL inputs and outputs, while the QDR II uses a 1.8 V core power supply with HSTL inputs and outputs. Again, if you were clever enough to put an LDO in line here on the initial QDR design, a swapped-out LDO for the QDR II will do as long as the timing and clocks can line up.
This is helped by the on-chip Delay Lock Loop (DLL) and the synchronous internally self-timed writes. But read or write only operations at any one time will not see bandwidth benefits from the QDR parts. The increased bandwidth is achieved by supporting separate data inputs and outputs for simultaneous read and write operations. If you are not doing simultaneous reads and writes, the efficiency goes way down, and QDR may not be a good fit.
But in streaming applications, networked packet processing, constant-bit-rate telecom, and other applications where data are moving in and out constantly, QDR may be best. The independent ports transfer data with a double-data-rate interface that results in a 4× improvement in data throughput vs. comparable synchronous SRAMs.
Jointly specified and developed by Cypress, IDT, NEC, Renesas, Samsung, and formerly Micron, means that pin-compatible products from multiple world-class suppliers assure 100 percent compatible alternate sourcing. Packaged in a 13 × 15 mm, 1.0 mm pitch FBGA package, 165-ball (11 × 15 matrix), these new parts take advantage of the variable-drive HSTL output buffers to help assure an easier interface to bolt-on processors, ASICs, and FPGAs.