Crossware's 8051 development suite now supports Philips and Atmel W&M 89C51Rx2 variant flash microcontrollers. These chips include up to 64KB of reprogrammable flash memory, into which the Crossware system loads a small debug monitor. The monitor enables source-level debugging. It will program the software into flash and run it at full speed, while allowing the user to halt its execution at any time and single step or trace through the code. The environment also simulates the reprogramming protocol, enabling programmers to test it using simulation before running it with the hardware. The 8051 development suite includes an ANSI C compiler, a relocatable cross-assembler, an advanced overlay linker, a source-level simulator that can be extended to simulate a complete target system, and debug tools.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.