The AT94s family of single-chip programmable SoCs integrates 246Kbits to 1Mbit of configuration EEPROM, a 20MIPS RISC processor; 5,000 to 40,000 FPGA gates; 20KB to 36KB of SRAM; and peripherals, which include UARTs, timer/counters, a 2-wire serial interface, and a hardware multiplier. Additional peripherals and co-processor functions can be created in the FPGA and mapped into the address space of the microcontroller. The AT94S family does not require external memory to store the FPGA configuration data and processor program code. The family has a patented security feature to protect the FPGA configuration and microcontroller program data from being read from the configuration EEPROM. A security bit on the device can be set during programming to prevent the memory from being read back statically or during internal configuration of the FPSLIC device. Once the security bit is set, the only means of externally accessing the FPSLIC configuration EEPROM is to erase it first. According to the company, the AT94S is rated at 0.05mA maximum in standby mode and 2mA/MHz while active. AT94S devices are available now starting at $6.50.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.