SAN JOSE, Calif. In an effort to move deeper into high-speed networking gear, Xilinx Inc. this week will roll the first batch of FPGAs that pack embedded PowerPCs and serial I/O transceivers running at 3.125 Gbits/second. Xilinx plans to incorporate up to four CPU cores and 16 transceivers on the same die, making the new family the most ambitious FPGA design since the launch of the company's popular Virtex line.
One of the chief technical achievements of the Virtex-II Pro is the way it integrates the 300-MHz PowerPC 405 cores. Xilinx took the unusual step of enveloping the core within the FPGA fabric itself. The hard processor cores are immersed within the first four layers of metal; above them are an additional five layers of routing. In this way, all 700 I/O nodes of the processor core can be accessed through the FPGA fabric.
This differs markedly from the approach of rival Altera Corp., which placed an ARM9 hard core at the edge of its programmable-logic array in the Excalibur product line. It's still too soon to know with certainty which architecture is superior, but some believe Xilinx could have the edge.
"If it [the processor core] were on the side and you had to get signals from one side to a far corner, physically you would have a long way to go," said Cary Snyder, an analyst with MicroDesign Resources. "By cutting it out in the middle, the physical properties favor that as being the more desirable method. It looks like a more elegant solution."
A second major innovation is the inclusion of I/O transceivers that can scale from 622 Mbits/s to 3.125 Gbits/s. Four of these transceivers can be channel bonded to make a single 10-Gbit/s pipe, which would suit the Virtex-II Pro for ultrafast Internet backbones that connect to a final optical driver. "There's nothing in the world that is out there or on the drawing board that we can't connect to," said Willem Roelandts, president and chief executive of Xilinx, based here.
To pull it off, Xilinx sought the aid of several other companies to synchronize all the hardware and software components going into its FPGA platform design. The company licensed the PowerPC 405 from IBM Corp., which also provided the CoreConnect on-chip bus. For the transceivers, it uses technology from Mindspring Technologies, and Wind River Systems Inc. supplied help with the software.
The devices will be fabricated by IBM Microelectronics' foundry service, although Xilinx plans to use its main foundry partner, United Microelectronics Corp., for volume production, said Erich Goetting, vice president and general manager of Xilinx's Advanced Products Group.
Goetting said Xilinx chose the PowerPC because the 32-bit CPU is showing up in embedded networking applications more often than its next-closest rival, MIPS. Moreover, Goetting said, Xilinx was worried that MIPS Technologies Inc., which has a relatively small market cap, could one day be the target of an acquisition, an event that could throw the future of the MIPS instruction-set architecture into doubt. By contrast, both IBM and Motorola Inc. have vested interests in the PowerPC, he said.
The 32-bit 405 core runs at 300 MHz and is estimated to have a performance rating of 420 Dhrystone Mips. This is a reasonable level of performance for the application segment the device is targeting, though it's not considered leading-edge performance for the 0.13-micron process technology it is based upon, analyst Snyder said.
Yet Xilinx said the PowerPCs on board the Virtex-II Pro aren't necessarily intended to replace every discrete processor on a board. Instead, they can serve to augment programmable-logic functionality without taxing an external CPU. One embedded 405 processor and on-chip block RAM within the FPGA, for example, could be used as a small packet-processing engine that handles exceptions or in-system statistics monitoring.
"We're not saying every processor needs to be replaced. But now a CPU can be dedicated to a specific task," Goetting said.
Xilinx is tapping IBM's CoreConnect on-chip bus to tie together the CPUs with other cores and peripherals, although Xilinx says Virtex-II Pro could also use alternative on-chip buses. Implemented as a soft core within the FPGA fabric, the bus runs at 133 MHz itself an impressive technical achievement, noted MicroDesign's Snyder. Xilinx has been busy targeting its own intellectual-property portfolio to the bus, which essentially means that Xilinx IP will be compatible with the IP being used in devices coming out of IBM Microelectronics, the leading ASIC manufacturer. Moreover, Xilinx says it will provide a special tool called ChipScope to let developers monitor and analyze individual signals and bus transactions coming off CoreConnect.
To further facilitate higher levels of design, Xilinx has added a tool that automatically generates the hardware-design-language and software code. With this high-level "automatic system generator," users can specify the system architecture, configure peripherals and assemble a system using a pushbutton Windows environment before hardware and software partitioning.
To move data on and off the chip at fast serial rates, Xilinx licensed the SkyRail transceiver technology from Mindspring and added its own configurable support circuitry. The transceivers act like a standard serializer/deserializer transceiver, and include the physical-coding sublayer and physical-media attachment. Additionally, they support 8B/10B encode/decode, output pre-emphasis, channel bonding and comma detect. For software support, Xilinx leaned heavily on partner Wind River Systems, which is porting real-time operating systems and development tools for the Virtex-II Pro's PowerPC. They include a C/C++ compiler for the PowerPC, a software debugger and a JTAG hardware probe. Xilinx is also providing its own version of the GNU tool chain for the Pro series.
The three Virtex-II Pro devices available today contain between 6,768 and 20,880 logic cells, one to two processors and four to eight multigigabit transceivers. Depending on the configuration, estimated volume pricing for devices scheduled to ship in the fourth quarter will be $120, $180 and $525. Xilinx also plans to introduce by the fourth quarter a four-transceiver device without a processor and a four-processor, 16-transceiver FPGA.