TOKYO Toshiba Corp. will take the wraps off a configurable processor core that can be customized according to application at the Embedded Processor Forum this week in San Jose, Calif. The company plans to promote the MeP for "media embedded processor" as a de facto standard embedded solution for multimedia use.
Toshiba will offer MeP in two forms: as a family of system-on-chip ICs; and as licensable intellectual property (IP). A low-power version is scheduled to hit the market this year. For IP sales, Toshiba said it might recruit third parties to prepare a design environment.
Based on Toshiba's original 32-bit RISC architecture, the MeP core uses 16- and 32-bit variable-length instructions, and has 16 general-purpose registers, as well as a five-stage pipeline.
Depending on the application requirements, the core can be configured using varying instructions, memory configurations, debug support, interrupt controller, timer/counter and bus interface width.
Extensions in the form of hardware and software IP can be added to form "MeP modules." Extensions include user custom instructions, a DSP unit, hardware engines and a very long instruction word coprocessor. MeP modules with different functionality, such as video and audio decoders, are linked to a global data bus to form a one-chip system.
Toshiba started MeP architecture work around 2000 and developed an MPEG-2 high-definition decoder last year. Now the MeP engineers are working on a low-power version, called c2, using a 0.13-micron process. MeP-c2's minimum configuration has 46,000 gates, operates at 200 MHz (worst case), and packs a 2-kbyte Level 1 cache and 16 kbytes of data RAM.
Power consumption is 0.11 milliwatt per megahertz, which Toshiba said is about one-third the average power consumption of several 32-bit processors with the same size memory.
More Embedded Processor Forum coverage.