The MCF5249 core features up to 125 Dhrystone 2.1 MIPS at 140MHz. It includes 96KB of on-chip SRAM, 8KB of instruction cache, and the following peripherals: two independent UARTs, two 16-bit timers, phased-lock loop clock, software watchdog timer, general purpose input/output lines, two I2C interfaces, queued SPI interface, four-channel direct memory access, and a glueless SDRAM controller. It's available now for $10.30 apiece in quantities of 10,000.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.