SAN MATEO, Calif. A major upgrade of Xilinx Inc.'s Integrated Software Environment FPGA design tool package features new system-level design capabilities, improved performance and new utilities to simplify FPGA design.
Rich Sevcik, senior vice president of FPGA products, said that with more than 300 software engineers working in its tool R&D department, the company has added significant new functionality to the Integrated Software Environment (ISE) and has streamlined the tool flow so designers can more easily work with the latest Xilinx devices.
The software being developed not only matches ASIC design tools, Sevcik said, but may also be more advanced. "Because we already know our targeted silicon architecture," he said, "we don't have to focus our efforts on developing software to ensure the silicon works. We can focus our efforts on developing software that allows engineers to more rapidly create designs on silicon they know will work."
Xilinx intends to take the lead in system-level tool development, Sevcik said. Starting with this release, ISE version 5.1i, and continuing through the end of the year, he said, Xilinx is adding new embedded tool capabilities to the software.
Sevcik said the company is working with third-party vendors to further a design methodology based on on-demand architectural synthesis, allowing designers to define system functionality at a high level of abstraction, then debug, synthesize and verify a range of architecture implementations that meet system specifications.
The new methodology will let designers determine the optimal hardware implementation, and changes in hardware/software partitioning to achieve the best cost/performance, without having to modify the source specification, Sevcik said.
Xilinx has already announced the System Generator for DSP, which lets designers model a DSP system and generate an FPGA implementation using The MathWorks Simulink and MatLab tools, Sevcik said.
Xilinx had also announced it is working with Synplicity for physical synthesis, Wind River Systems for embedded design support, Monta Vista for embedded Linux support and Mentor Graphics for co-verification support. He said the company will release more information about its work with an unnamed "leading EDA partner" to jointly develop an architectural synthesis tool.
Sevcik acknowledged that even these new tools do not yet allow a software engineer to program both the hardware and software of a Xilinx device, but said that is the dream of the company, since it would give Xilinx an opportunity to sell its devices to hundreds of thousands of software engineers.
"For now, we are concentrating on allowing a system architect, who knows both hardware and software, to program a Xilinx device," said Sevcik. "We hope to eventually develop tools that will allow a software engineer to program the hardware and software of one of our devices, but that is still a ways away."
But the latest rev of ISE adds a slew of optimizations and new functions:
Better place and route algorithms and correlation with third-party synthesis tools to get a 2x improvement in compile times (an increase from 100,000 to 200,000 gates/minute);
A 40 percent gain in device speeds over last year's software release;
An incremental design capability so last-minute changes can be made without jeopardizing a device's development schedule.
Xilinx also added a utility called the Advanced Pinout and Area Constraints Editor (Pace) management tool to simplify the specification of device I/O, including interactive voltage banking, and differential pair identification guidelines.
ISE 5.1i also has new wizards: The Digital Clock Managers (DCM) wizard and Rocket I/O multigigabit transceivers (MGT) wizards. They let users graphically set DCM and MGT functions through dialog boxes in the ISE Project Navigator.
ISE then writes editable source code directly into the HDL source file to set and control those advanced capabilities. Sevcik said the wizards guide users in HDL coding, alleviating the need to learn all of the programming attributes required to configure complex device features, thus speeding the design process.
Another new utility is the Macro Builder. The feature is accessible in ISE Floorplanner and allows users to designate any chunk of their design as a core, use the tool to harden that core in terms of timing and layout information. The core can then be moved to other parts of their design or passed to other design groups for design reuse.
In addition to the new utilities, ISE 5.1i also includes HDL coding-style checkers from Atrenta and Synopsys. Sevcik said Atrenta's SpyGlass now supports ISE 5.1i by offering predictive HDL analysis for Xilinx's FPGAs.
Pricing for ISE starts at $695. The 5.1i version of ISE WebPack will be available for free download in October.