San Mateo, Calif. - FPGA tool startup Hier Design Inc. will launch a silicon virtual-prototyping (SVP) tool this week that applies the advanced methodologies of the ASIC world to high-end field-programmable gate array designs, the company said.
PlanAhead, Hier Design's first product, is the kind of SVP tool previously available only to ASIC designers, said Jackson Kreiter, chairman and chief executive officer. But FPGA designers now need SVP as products grow faster, more complex and reach multimillion-gate densities, Kreiter said. Some of the developers of Monterey Design Systems' Sonar ASIC floor-planning tool founded the Santa Clara, Calif., company in 2001.
"With PlanAhead we are bringing an ASIC-style methodology to high-end FPGA designers," said Kreiter. "Just like in the ASIC world, we are giving users the capability to understand the performance of a design prior to place and route."
PlanAhead will shorten a design cycle by reducing the number of synthesis-to-place/route iterations an FPGA designer needs to perform, Kreiter said. The tool in its present form is targeted exclusively at ASIC designers moving to FPGAs and high-end FPGA designers tackling projects of more than 1 million gates, he said. But if FPGA gate counts continue their rapid climb, Kreiter said, the mainstream market could come in range of Hier's target.
Like ASIC SVP tools, the PlanAhead floor planner provides designers with insight into the placement and routing process. Designers feed an EDIF netlist, generated with an FPGA synthesis tool, into PlanAhead along with Synopsys Design Constraint formats or Xilinx timing constraints. The tool will autopartition or manually partition the design project into hierarchical blocks to find the optimum floor plan for the FPGA design. It outputs an EDIF netlist optimized for an FPGA vendor's placement and routing environments.
PlanAhead displays device resources, connectivity and logical and physical hierarchy, allowing designers to visualize problem areas. Kreiter said users can create and manipulate physical hierarchy independently from logical hierarchy, and simultaneously plan and analyze multiple physical implementations to find the best layout.
PlanAhead also has a manual or automatic physical block-sizing and placement feature, along with a clock I/O and clock-region-planning feature.
A design team leader could also use the tool to chop a design into several blocks, assign the blocks to various designers in a group, then reassemble them in the PlanAhead environment, Kreiter said. Users can place unfinished blocks in a design before all the blocks have been assembled to get an early jump on a layout.
PlanAhead's design analysis capabilities address timing, connectivity, utilization, I/Os, clock regions and carry chains. Power and other analysis capabilities will be added soon, the company said.
Kreiter said that on a recent design project, a beta user of PlanAhead was able to shrink the size of nonessential blocks in a design that had a 101 percent utilization rate-requiring a second FPGA-yielding a device with a 96 percent utilization rate, while also meeting performance goals.
"This couldn't be done with even the best FPGA physical synthesis tools," he said. "Those tools flatten out a design and then run physical synthesis on the entire flattened design. They can take days to finish a million-gate FPGA design. Our flow allows users to pinpoint those trouble areas and optimize them to cut down on overall design time."
PlanAhead currently does not have a back-annotation capability, Kreiter said. The tool generates reports that indicate a design's problem areas, for example, but does not backtrack to the RTL to pinpoint where in the code the problems cropped up. But Hier Design hopes to have such a feature in a future release, Kreiter said. The company also plans to add some physical synthesis capability, or to link to an established physical synthesis tool, giving designers an ability to resynthesize problem areas in a design.
Synplicity Inc.'s Amplify FPGA physical synthesis tool, for example, can perform local synthesis, which spares designers from resynthesizing an entire design.
Hier Design is charging $25,000 for a one-year subscription license to PlanAhead.