On the heels of its just released MachXO crossover programmable logic devices, Lattice Semiconductor Corp. is making available under an open IP core license its LatticeMico8, an 8-bit "soft" MCU core for its various families of PLDs and FPGAs.
Available for use on the LatticeECP, LatticeECT, LatticeXP families of Field Programmable Gate Arrays (FPGAs), as well as the recently released MachXO, the open intellectual property license is being offer to encourage user experimentation, development and contributions, according to Stan Kopec, Lattice vice president of corporate marketing.
Claiming it is the first such license offered by any FPGA supplier, he said the license applies many of the concepts of the successful open source movement to IP cores targeted for programmable logic applications.
Kopec said the LatticeMico8 microcontroller consumes less than 200 Look Up Tables (LUTs) in the smallest configuration, while maintaining a broad feature set, including: 18-bit wide instructions; 32 general purpose registers, 32 bytes of internal scratch pad memory, Input/output performed using "ports" (up to 256 port numbers); two cycles per instruction; a Lattice UART reference design peripheral and an optional 256 bytes of external scratch pad RAM.
In addition to offering the core design in Verilog, Lattice is also offering an assembler and an instruction set simulator, both as source code. To showcase the features and capabilities of the LatticeMico8, a demo is available for download that allows users to implement a working design in less than 30 minutes on a Lattice evaluation board.
To further enhance flexibility, the design is parameterized to allow the easy implementation of four configurations, each optimized for different user needs.
Downloadable from the Lattice Web site, Kopec said the open IP license agreement addresses specific issues associated with designs targeted toward programmable logic.
Specifically, he said, the license has been written to preserve the open nature of the core by permitting use alongside proprietary designs and to allow hardware implementation and distribution without the need for a license agreement
Additionally, both the Assembler and Instruction Set Simulator will be available as source under the standard GNU General Public License (GPL) agreement.