STMicroelectronics has completed validation and released its SPEAr Head, a new member of the company's Structured Processor Enhanced Architecture family of configurable System-on-Chip ICs.
The new SPEAr Head (part number SPEAr-09-H020) integrates an advanced ARM926EJ-S core running at 266MHz, a complete set of IP (intellectual property)
blocks and a configurable logic block, making possible fast customization of critical functions in a fraction of the time and cost required by
a full-custom design approach.
According to Vittorio Peduto, General Manager of ST's Computer Systems Division, the new device includes an ARM926EJ-S running at 266MHz with 32 Kbytes of Instruction cache, 16 Kbytes of Data cache, 8-Kbyte Data-TCM (Tightly Coupled Memory) and 8-Kbyte Instruction-TCM.
It also incorporates a number of I/O capabilities including three USB2.0 ports (two hosts and one device supporting high speed mode) and an
Ethernet 10/100 MAC as well as a 16-channel 8-bit A/D converter; an I2C interface; three UARTs; SDRAM memory interfaces at 133MHz supporting DDR and SDR; and an SPI interface supporting serial FLASH/ROM.
Samples of SPEAr Head are already available, with pricing in the range of $12 in volume quantities. Full development boards will be shipped in December. A
special dual-mode development environment has been implemented to allow use of an ASIC-like design approach or to implement an external FPGA.