Mirabilis Design Inc. has just released the first in a series of hardware and software model generators for the VisualSim Architect support detailed cycle-accurate simulation models of microprocessors, microcontrollers, DSP and application-specific processors in less than one day using only parameters.
According to Deepak Shankar, President of Mirabilis, the Processor Generator Toolkit is designed to let processor architects optimize the pipeline and instruction set and allow systems engineers to design new system platforms and software engineers to experiment with flows, thread distribution and scheduling long before an architecture commitment is made.
The Processor Toolkit works by describing a processor using information from the vendor datasheet. This data is input into a wizard containing parameters, instruction table and pipeline stages.
The resulting processor model is used to define complete systems with the Architecture Library components- RTOS, bus, switch, DRAM, DMA, controller and cache. Software instruction sequences and pseudo-code can be executed on this model for performance and power evaluations of multi-processor or multi-core systems.
The generated processor model provides full visibility into the pipeline, execution units, instruction set, pre-fetch actions, data and instruction cache access, superscalar, out-of-order executions and interrupts service routines. Analyses include latency by transaction, route mapping, utilization by individual unit, stalls, flush time, context-switching, hit-miss ratio and throughput.
VisualSim Processor Generator Toolkit is part of the Architecture Library. It works with the company’s VirtualSim Architect and is currently available on Windows, Linux and UNIX.
Architect is a graphical, platform-independent design environment that accelerates performance analysis and architecture exploration. Designers construct models using pre-built parameterized construction components and use the automated statistics and run-time visualization for ad-hoc analysis.
The tools are fully integrated SystemC and all mathematical capabilities of MatLab. In addition, there are co-simulation links to Verilog, VHDL, STK, Excel and MatLab and an open, timed-API for integrating simulators. VisualSim optimizes the initial concept through a series of modeling refinements and abstractions to allow the best architecture to become an executable specification.
VisualSim Architect is a prerequisite for the Toolkit. Pricing for the Processor Generator Toolkit starts at $5000 including parameter settings for PowerPC and ARM. Other processor parameters can be defined by the user or are available at no extra charge from Mirabilis Design.