If Brett Favre was a design engineer, he'd love Cypress Semiconductor's Programmable SoC family. Favre, the now-I'm-playing, now-I'm-retired, now-I'm-back-again quarterback of the Vikings has made indecision a national sport and with PSoC's flexible visual embedded design methodology that includes preconfigured, user-defined peripherals and hierarchical schematic entry, engineer Favre could can change his mind to his heart's content and still have a reasonable shot of keeping his design project on schedule.
For the uninitiated, the PSoC architecture is a programmable embedded system-on-chip integrating configurable analog and digital peripheral and memory blocks with a microcontroller. In the case of the new PSoC 3 the MCU engine is an 8-bit 8051 at 33 MIPS while a 32-bit ARM Cortex-M3 core capable of up to 100 Dhrystone MIPS powers the new PSoC 5.
Here's one thing you should immediately notice: both platforms meet the demands of extremely low power applications by delivering what Cypress says is the industry's widest voltage range, from 5.5V down to 0.5V, along with low 200nA hibernate current.
Perhaps the most useful feature of PSoCs is the flexibility they provide to make firmware-based changes during design, validation and even production. This shortens design cycle times and facilitates updating a design at any stage of the design process to accommodate changing feature requirements.
The PSoC's digital subsystem provides half of its useful configurability. It connects a digital signal from any peripheral to any pin through the Digital System Interconnect (DSI). It also provides functional flexibility through an array of small, low power Universal Digital Blocks (UDBs). Each UDB contains Programmable Array Logic (PAL)/Programmable Logic Device (PLD) functionality, together with a small state machine engine to support peripherals.
The analog programmable system creates application specific combinations of analog signal processing blocks. These blocks are interconnected to each other and also to any pin on the device, providing a high level of design flexibility (as well as IP security). The features of the analog subsystem include (using the PSoC3 CY8C34 as an example): a Delta-Sigma ADC, two 8-bit DACs, four comparators, two configurable switched capacitor/continuous time blocks for functions that include op amp, unity gain buffer, programmable gain amplifier, transimpedance amplifier and mixer, and two op amps for internal use and connection to GPIO pins. In addition, a CapSense subsystem enables capacitive touch sensing.
New design software dubbed PSoC Creator combines a software development IDE with a graphical design editor to form a hardware/software co-design environment. Users simply lay out the design, just as they would on paper or a whiteboard, and let the tool translate it into the PSoC configuration. It provides a library of pre-built and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, timer, counter, PWM, AND, OR, and so on) that are mapped to the UDB array. The tool automatically routes all on-chip signals and can even direct I/O to the optimum pins if desired.
Cypress also offers free compilers without code size limitations for both PSoC 3 and PSoC 5 devices. The Keil CA51 Compiler for PSoC 3 and the GNU GCC-ARM Compiler for PSoC 5 are both bundled with the PSoC Creator distribution. PSoC Creator also includes a built-in debugger to support the on-chip debug and trace functionality provided in all PSoC 3 and PSoC 5 devices.
Real-Time Operating Systems (RTOS) supported include Keil RTX51Tiny, Micrium mC/OS-II, and SEGGER emboss. PSoC Creator is expandable so new compilers, editors and Real-Time Operating Systems can be added in the future.