Wolfgang Roethig, Senior Engineering Manager, EDA R&D Group, NEC Electronics Inc., Chairman of Accellera's Advanced Library Format (ALF), Santa Clara, Calif.
Traditionally, ASIC design has been focused almost exclusively on timing closure. Heuristic rules and guard bands were used to protect the design against adverse effects on signal integrity, such as noise or electromigration. However, it is well known today that such guard bands are no longer sufficient; they have prevented the efficient use of technology to the point that clock frequencies above 200 MHz could be reached only with difficulty on ASIC-style designs.
Therefore, point tools have been introduced into the design flow to analyze signal integrity more accurately, looking at such issues as crosstalk-induced noise, electromigration, hot electron and antenna effects.
In addition, static timing analysis has been enhanced to consider crosstalk-induced delay. Conventional crosstalk-aware timing analysis is done by an iterative combination of delay calculation and static timing analysis. To calculate crosstalk-induced delay, the arrival times of aggressor and victim must be known; to calculate arrival times, delay must be known. Convergence is reached after a certain number of iterations between delay calculation and static timing analysis.
In this approach, timing, noise, electromigration, hot electron and antenna effects are checked and eventually fixed through scripts prescribing incremental layout changes. The point tools are mutually unaware of other effects. Therefore, fixing an electromigration violation may cause a timing violation and vice versa.
For high-end designs in system-on-chip style, the method of iterative analysis and repair of signal integrity violations by independent point tools is inefficient. The analysis and repair functionality has to be integrated into the same tool.
The quality of results depends on the quality of the analysis models that are provided to the tool. These models reside in a technology library, described in the Advanced Library Format (ALF), an emerging IEEE and IEC standard. ALF is the only available industry standard that can describe not only timing, power and noise, but also electromigration, hot electron, antenna and more in a comprehensive and unified way.
For technologies of 0.18 micron and smaller, the shape of the signal waveform plays a significant role in describing the timing characteristics. A driver resistance model can predict the shape of a waveform and its distortion by noise. Eventually, multiple signals on coupled nets switch simultaneously and cause mutual waveform distortion. The driver resistance model makes it possible to calculate the resulting waveforms using linear circuit analysis.
Those waveforms depend also on the alignment of the original ones. If pessimistic time windows are used, the waveform alignment is not known with much certainty. Therefore, the concept of activity windows is introduced. The idea is to calculate multiple narrow time windows of possible switching activity per clock cycle in order to decide with more certainty whether aggressor and victim waveforms will overlap or not.
Each activity window is associated with bounds for output arrival time, slew rate and driver resistance. These parameters are calculated from input arrival time and slew rate, using timing models in the ALF library.
The driver resistance for steady state is used for noise calculation on a quiet victim driver cell. In addition, a noise margin on a victim receiver cell is provided.
A criterion for a tolerated noise peak at an output pin of a cell defines the noise margin at a related input pin. The noise peak at the output depends not only on the noise peak at the input but also on the pulse width and the effective output load capacitance. A narrow pulse is subjected to low-pass filtering. This effect is called noise rejection.
For combinatorial cells, noise activity at the output can be tolerated so long as it does not corrupt the data of a memory element, a flip-flop or a latch. Therefore, noise propagation through combinatorial cells can be described in the library.
Electromigration occurs inside cells as well as on interconnect structures. It is due to high current density, causing wires and contacts to break eventually. The structures inside the cell tend to break first, especially the contacts at the driver output.
Other damage occurs due to the hot electron effect. This manifests itself by accumulation of trapped carriers in the gate oxide, leading to threshold changes and performance degradation. Both effects can be evaluated by transistor-level analysis. However, for large circuits, a cell-level abstraction model is needed.
The abstraction consists of a vector defining the activation stimulus for a path. Associated with the vector is an upper limit for tolerable activation frequency of the vector. This frequency limit is an abstraction of the tolerable electromigration or hot electron damage, which depends on input slew rate, output load or both.
Since a vector can contain temporal and logical dependencies, it is possible to represent electromigration and hot electron constraints affecting internal structures of a complex cell by vector frequency limits describing events and states observable at the boundary of the cell.
A new design flow using ALF would apply a physical optimization tool conscious of all signal integrity effects: in particular, timing, noise and electromigration. Driven by its own concurrent timing and signal integrity analyses, the tool would implement design changes with minimal disturbance. As a result, the number of design iterations would be greatly reduced. For instance, crosstalk-aware static timing analysis supports multiple activity windows within a clock cycle. The analysis is driven by an ALF library, which contains models for timing, noise, electromigration and hot electron effects.
As with any design flow, external constraints must be provided. In addition to system-level timing constraints, a global activity file is provided for electromigration/hot electron analysis. This file contains estimated or simulated vector frequencies for each cell instance within the design; the frequencies are compared against the vector frequency limits in the library. For a given vector frequency, the slew- and load-dependent frequency limit translates into a slew-dependent load limit on a cell instance.
The success of the design flow relies on accurate libraries. A suite of benchmarks with normative Spice results has been applied to qualify the ALF library within the context of its usage by the tool. For example, the ALF timing library alone, by virtue of including more precise data, yields significantly better accuracy than a conventional timing library. The average error of ALF vs. Spice was 0.5 percent, compared to 4 percent, when a conventional timing library was used. The standard deviation was 2 percent compared to 5 percent. For noise and electromigration, there was no conventional library that could represent the data.
Based on its comprehensive modeling capabilities and the availability of supporting analysis and optimization tools today, ALF is well positioned as industry standard for high-end SoC design libraries.
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