To keep pace with ever-increasing line rates, networking communication designers will be one of the first sectors to push networking ASIC designs into the 130-nm range now and the 90-nm range in the near future. But, making the leap to smaller geometries will be wrought with challenges, such as crosstalk effects, IR drop, power dissipation, and electromagnetic interference.
Crosstalk is a particular challenge in high-speed networking IC design. To deliver true gigabit performance, designers need to effectively mitigate crosstalk problems. To do this, designers have traditionally turned to off-the shelf EDA tools from companies like Synopsys and Cadence. But off-the-shelf tools tend to take a pessimistic view of crosstalk, identifying all potential problems while designers actually look for only the problems that are impacting their current design.
To bridge this divide, designers can combine techniques, like buffer insertion, with existing tools to improve the overall crosstalk mitigation. Let's examine these techniques and see how they impact crosstalk mitigation.
Signal IntegrityWhat's it all about?
Signal integrity measures how faithfully the original signal is recovered from the imperfect transmission in a noisy environment. Put another way, signal integrity measures how well the output from a system matches the desired or expected output for any given input.
Maintaining signal integrity during the ASIC design process is crucial to achieving targeted performance within the project schedule. Technology scaling, increased clock frequencies, and higher levels of on-chip integration have a substantial impact on noise and signal integrity.
Technology scaling has made interconnect and device packaging increasingly important considerations, while faster clock and signal edge rates have resulted in increased signal coupling. At the same time, lower supply voltages are making noise of increasing concern.
Addressing this multitude of design constraints early in the ASIC design process with sophisticated simulation programs enables OEM designers to shorten their design cycles while optimizing the final IC product.
Handling the Crosstalk Problem
Clearly, crosstalk is one of the biggest signal integrity challenges designers must deal with when making the leap from 130- to 90-nm technology during the development of multi-service ASICs for networking applications.
Crosstalk is defined as the noise induced by the parasitic coupling between on-chip wires. This coupling reflects the non-ideal nature of the physical world in which the chip is fabricated and then affected by structural factors including the proximity of the wires, the physical dimensions of the wires, and the material used for and around the wires. The chip is also affected by logic factors such as the functionality of cells on the chip and the interaction between the desired logic signals on the chip. Structure and logic factors can interact to complicate crosstalk analysis.
Induced noise from crosstalk affects signal integrity and chip performance in several ways. Glitches, for example, can occur when the victim signal is in steady state 0 (low or off) or steady state 1 (high or on). In general, signal transition time for any circuit is much smaller than the time a signal is in steady state. Typically, signals tend to stay in steady state most of the time. Glitches, however, can disrupt this steady state, forcing designers to be more concerned about glitch noise in the IC design process.
Crosstalk noise can also happen when the signal is in transition from 0 to 1 or vice versa, creating transition noise that may cause a signal to switch slower, faster, or have non-monotonic behavior, ruining or disrupting its functionality. Incremental delay analysis captures the noise effect when transition noise causes a signal to switch slower or faster. When the noise causes the signal to be non-monotonic, a false pulse may be generated.
Making Realistic Noise Measurements
To detect realistic, detailed, and accurate crosstalk effects on a chip, knowledge is required about the chip at the logic, layout, and extraction levels. Some structural information about a circuit is available in the extracted view of the design and some logic information can be deduced easily from the cell function used in the design. However, chip designers best known the nitty-gritty details of a specific chip design. The challenge is making this vast amount of information available to the analysis tools.
Based on extracted parasitic data alone, designers working with crosstalk analysis tools have to assume the worst-case scenario for setting up the analysis conditions. Analysis conditions include if, when, and in which direction a signal can switch. The most pessimistic assumption is that any aggressor or problem-causing signal will switch, and at the worst possible moment, in the direction that causes the worst possible crosstalk noise.
Need to be more Optimistic
While a crosstalk analysis tool should not produce optimistic results, which would lead to actual circuits that fail, the pessimistic assumptions built into today's tools result in too many "reported" crosstalk violations, including true violations and false violations (false positives). Repairing all the violations flagged by the pessimistic analysis software is prohibitively expensive in design time, chip area, and power.
In addition, most crosstalk failures are data-pattern dependent; it is not possible to detect them at test time. As a result, the failures occur when the chip is already in the customers' systems and are very expensive to address. Therefore, it is important to identify and fix all true crosstalk related violationsthose that really affect chip performance.
To fix all crosstalk violations, IC designers need methods for reducing the false pessimism in the analysis process. Additionally, they need tools that focus on the true crosstalk problems and that automate the repair process.
Merging Tools with Layout
To solve some of the traditional crosstalk analysis problems designers can integrate crosstalk mitigation approaches by employing commercially available EDA solutions coupled during the IC layout process. Figure 1 shows an example of one current design flow for signal integrity using one set of available tools (note: purple shaded boxes contain Agere Systems specific software). Other tools can also be used, both commercially available and proprietary.
Figure 1: Design flow for mitigating crosstalk issues in ASIC designs.
The design flow depicted here starts with the place and route functions being done in Apollo/Astro from Synopsys. The IC design is stored in the Milkyway database. The left side of the diagram shows the parasitic extraction engine, StarRCXT from Synopsys, used to create a file in the SPEF format, which is an IEEE standard format.
The SPEF file is then input into two crosstalk analysis engines, AssuraSI or CeltIC, both from Cadence. These crosstalk analysis modules process the SPEF file and produce two sets of outputs.
The first output is an incremental standard delay format (SDF) file, which is the variation in timing due to crosstalk. This file, in turn, becomes input to the static timing analysis module, PrimeTime from Synopsys, which is shown on the left of Figure 1. PrimeTime also creates inputs into the crosstalk flow.
The second crosstalk analysis output is a glitch report. This report shows glitch values on victim nets.
There are different types of glitches. Overshoot and undershoot glitches are those where the signal on the victim net goes above and below the power supply and ground voltages, respectively. These glitches could cause functional failures on flip-flops and latches that have transmission gate inputs. The state stored in the gate can be destroyed, rendering the gate useless.
Ordinary glitches can propagate through multiple gates and get clocked into flip-flops, causing a functional failure. Small glitches on clock pre-drive nets can get amplified in downstream gates and can result in spurious clock pulses. These also lead to functional failures.
Figures 2 and 3 show various forms of crosstalk-induced glitches and delay variation.
Figure 2: Signals with glitches and delay variations.
Figure 3: Glitches on signals in transition.
The remaining parts of the flow shown in Figure 1 relate to methods for reducing the pessimism in the analysis (identifying true problems) and in automating the repair process.
The use of timing window information from the timing analysis tool, PrimeTime, is used to divide the aggressor signals into disjoint sets such that only the members in a given set can be active at the same time. The analysis is then run with each of the sets individually rather than with all aggressors acting together. This reduces delay variation and glitch magnitudes.
The signal partitioning function divides nets into disjoint sets where the signals in each set are active only at different times. For example, scan signals are active during chip testing, but can be considered static (not aggressors) as far as normal data signals are considered.
The glitch filters operate on detailed cell noise characterization data, working to eliminate glitches that cannot propagate through the cell. The noise threshold of the cell is dependent on the type of cell and its load. The combination of timing windows, signal partitioning, and noise filtering typically reduces the number of potentially harmful glitch violations from approximately 5.0% of the nets to about 0.5%. However, for a typical design with a million nets, this still leaves some 5,000 nets that need repair. Making all these repairs by hand is a tedious and error-prone task.
Chip designers can use four computer-based techniques to repair crosstalk violations. The software programs show the effects on noise and signal integrity achieved by 1) inserting buffers, 2) changing the wire spacing, 3) shielding the wires, and 4) changing the gate sizes. Let's look at each in more detail.
Buffer insertion is an effective repair technique to address capacitive crosstalk noise glitches and voltage over-and under-shoots that cause functional failure, delay variations, and race conditions. Yet after the place-and route process, the IC becomes very inflexible to design changes needed to accommodate the new buffers. Hence, fixing signal integrity problems becomes very challenging, particularly if the number of crosstalk victim nets is large.
The buffer insertion process shown in the design flow highlighted in Figure 1 performs "post place and route" buffer insertion that optimizes noise and delay parameters, while inserting as few buffers as possible. Buffers reduce the resistance-capacitance (RC) delay of nets by driving net capacitances through smaller resistances and by off-loading non-critical sinks from the critical path. Moreover, buffer insertion helps to mitigate crosstalk noise by weakening the affect of coupling capacitance, sinking downstream noise currents, and filtering upstream noise voltages.
The overall buffer insertion process is illustrated in Figure 4. As this figure shows, buffer insertion is accomplished by combining a tuning algorithm with crosstalk software (AssureaSI, CeltIC) into a convergent noise/timing-loop closure methodology (the right hand loop of Figure 4, dubbed the inner loop) that produces a fast and graceful reduction in the number of noise victims and significant improvement in the chip design turnaround time. This reduction occurs by eliminating loops through the place and route process (the outer loop in the figure). The outer loop needs to be run only after the inner loop has converged and produced a small number of noise victims.
Figure 4: Diagram of the buffer insertion process.
The buffer-insertion algorithm iteratively inserts a small number of buffers on crosstalk victims while gaining accurate feedback on crosstalk from the signal integrity tool invoked between iterations. As a result, the buffer-insertion process relies on accurate circuit simulation of the impact (on noise) of slowly adding buffers to victim nets.
Buffer addition is intentionally minimized because inserting a large number of buffers might trigger significant place-and-route perturbation, re-computation of layout parasitics, and signal integrity re-evaluation, thereby extending the design turnaround time. In addition, by adding too many buffers, the designer could convert victim nets to aggressor nets and thereby steadily increase the population of victims rather than decrease it. Fortunately, a vast majority of nets with crosstalk problems can be fixed by adding only a few buffers.
Adding a small number of buffers to a net topology that has already been placed and routed does not cause significant wiring detours and disruption when the routing is repeated. The chip design process flow described in Figure 1, therefore, avoids a time-consuming place-and-route step, followed by an expensive and possibly further time-consuming parasitic extraction process.
Experience has demonstrated that loop iterations are fast and the number of victim nets typically converges to a small value (less than 10 with circuits with 1 million nets) within six or seven inner loops. Moreover, there is excellent correlation between the noise victims predicted by the signal analysis software on the raw output of the buffer-insertion program and those predicted by the signal analysis software when the output of the inserted buffer is placed, routed, and re-extracted.
Table 1 gives the results for blocks of some production chips that had crosstalk problems. Table 2, on the other hand, shows the results for a single block over the inner loop iteration process.
Table 1: Results from production chips
||Number of Victim Nets
||Number of Iterations
||Time per Iteration
||less than 1 minute
||less than 1 minute
||less than 1 minute
Table 2: Results for a single netlist over the inner loop iteration process.
||Total Number of Victims
||Number of New Victims
||Number of Old Victims
||Number of Buffers Inserted
Wire Spacing, Shielding, and Gate Sizing
Spacing the wires apart or shielding the victim nets reduces the coupling capacitance and the induced glitch magnitude, thereby improving the signal integrity of a design at the potential cost of increased die size. Similarly, upsizing the victim gate makes the glitch magnitude smaller.
Figures 5 to 7 show how a wire spacing tool (X2), a wire shielding tool (WSD), or a gate sizing (GS) tool can be used in the IC design flow.
Figure 5: Wire spacing flow.
Noise Reduction by shielding wires.
Figure 7: Reducing crosstalk by gate sizing.
In a manner similar to the buffer-insertion process program, the design process depicted by the block on the right side of the Figures 5 and 7 changes the SPEF to mimic the action that will be taken by the router. The crosstalk analysis is then run again and, if the resulting glitch is acceptable, and if there is no adverse effect on timing, then the action is accepted. These actions are then converted into suitable commands for the router. No inner loop is required in the case of wire shielding.
The advantage of the inner/outer loop approach is that the time consuming trial loops through the router program are reduced. For example, in one ASIC design project using 160-nm process technology, a block with 215,000 nets had 390 glitch violations reduced to 11 with one pass of wire spacing scripts. In another case using a 140-nm process technology, an IC block with 103,000 nets had 94 glitch violations reduced to ten with one pass of the wire spacing loop, and then to three violations with one buffer insertion cycle.
Looking to the future
As we look at the future of semiconductor design, crosstalk induced noise is likely to be the dominant cause of chip failures at the 130- and 90-nm technology nodes. IC designers have benefited in the past from the many EDA tools introduced by design automation companies such as Synopsys, Cadence, and Magma.
But while these tools are crosstalk-aware during the place and route stage, they are not yet sufficiently mature and do not eliminate all crosstalk violations. They do, however, reduce significantly the number of violations. It is now possible to enhance these commercial tools with routines for buffer insertion, wire spacing, and more, to produce practical design solutions.
These superior design solutions, however, require significant effort both on the part of IC design houses in characterizing cell libraries for noise as well as the IC manufacturer in augmenting CAD vendor provided tools. The gains can be significant when dealing with highly complex ICs typical of next-generation communications silicon.
About the Authors
Don Friedberg is the director of design methodologies at Agere Systems. Don is a graduate of Rensselaer Polytechnic Institute and Syracuse University and can be reached at firstname.lastname@example.org
Kishore Singhal retired recently from Agere after 20 years with AT&T, Lucent, and Agere. He has had responsibility for analog and technology modeling, analog simulation, interconnect modeling, and signal integrity. Prior to joining AT&T, he spent 15 years at the University of Waterloo and was a professor in the Department of Systems Design Engineering. Kishore is an IEEE fellow and can be reached at email@example.com.