In the late 1990s, after more than a decade of ferroelectric-memory development, several companies succeeded in the high-volume production of low-density (less than 1-Mbit) ferroelectric RAM. These nonvolatile memories have an architecture similar to that of conventional DRAM; but in contrast to the charge storage mechanism associated with DRAM, ferroelectric memories store information through the use of a spontaneous, stable, electric dipole intrinsic to the ferroelectric crystal. When the ferroelectric is incorporated within a capacitor structure, the dipole's orientation can be reversed via the application of an external voltage.
At a conceptual level, FRAM can be viewed as DRAM with a nonvolatile capacitor element. Today's mass-produced, low-density FRAMs exhibit reliability properties, data retention and read/write endurance greater than 1014 cycles, making them suitable for a wide range of applications. As a result of their high read/write speeds and low power consumption, FRAM devices have found application in the smart-card, power, printer, videogame and RFID markets.
Two ferroelectric materials, lead zirconate titanate (PZT) and strontium bismuth tantalate, have been developed for FRAM applications. To date, most volume FRAM production has employed PZT.
During the same time period that FRAM was being developed, a seismic shift was occurring in the driver applications for semiconductor devices. The fastest-growing segments no longer revolved around the PC; rather, they focused on mobile communications, Internet and personal electronics that offer wireless interconnection. Examples include cell phones, personal digital assistants, digital cameras and camcorders and printers.
The desire for seamless connectivity of these various portable units necessitates the simultaneous device-level integration of traditionally disparate functions such as high-speed logic, RF transmission and reception, analog circuitry, power management blocks and dense memory. To succeed in this mobile Internet market, semiconductor manufacturers will need to provide these functions while minimizing chip power dissipation and cost. The ultimate goal of this effort is the creation of a single system that can realize all of the needed functions while providing the benefits of silicon scaling.
One of the most challenging areas for cost-effective system-on-chip (SoC) integration is embedded memory, because both high-speed operation and nonvolatility are required. SRAM has long served as the embedded memory of choice for logic chips, but its volatility, large size and standby current limit the total size of the memory.
Nonvolatile flash memory can be integrated within a logic process, but its high-voltage operation requires the fabrication of thicker gate oxide transistors and increases the chip cost by roughly 25 to 30 percent. Embedded DRAM has the smallest cell size, but data refresh constraints demand the co-integration of low-leakage transistors, leading to a similar 25 to 30 percent increase in chip cost. Further, embedded DRAM does not satisfy the nonvolatile requirement.
In recognition of these challenges, semiconductor companies have been evaluating and developing novel memory approaches for the past several years. Memories based on magnetic tunnel junctions (MRAM), phase-based resistance changes (OUM), ferroelectric switching (FRAM) and other physical phenomena have been pursued. For mobile Internet SoC applications, the key issues are nonvolatile functionality, low power consumption and minimal added process complexity.
To make the leap from existing low-density FRAM to cost-effective, high-density devices, several companies have developed novel process, integration and design approaches. First, the FRAM cell architecture has been modified from a two-transistor, two-capacitor (2T-2C) approach to a DRAM-like, 1T-1C configuration, reducing the cell area by a factor of two. Second, the capacitor has been placed directly on top of the contact plug to the drain of the pass transistor instead of over an adjacent field oxide. This change reduces the cell size by a further factor of two to four. Finally, FRAM is being developed at the 0.18- and 0.13-micron logic nodes, representing an additional 4x to 8x cell size reduction from currently available technology.
To date, the smallest FRAM cell size reported is TI's 0.54-micron2 design-roughly 30 to 50 times smaller than the currently produced 1T-1C and 2T-2C cells, respectively. For the 90-nanometer node, TI foresees embedded FRAM cell sizes down to 0.35 micron2, or roughly two to three times the density of SRAM.
A single-mask, capacitor-etch process, which increases the capacitor sidewall angle and allows capacitors to be more closely spaced, has been developed. And a new metal-organic chemical vapor deposition process for the ferroelectric films, which reduces deposition temperature while improving film quality, has been brought into preproduction. Films deposited by this method can be scaled to operate below 1 V.
An improved capacitor encapsulation process, which protects the ferroelectric capacitors from degradation during back-end interconnect formation, has also been implemented.
These process and design modifications have allowed high-density embedded FRAM and SRAM to be co-integrated on a single wafer using a five-level-metal, 130-nm core logic process. A 64-Mbit FRAM array has been constructed with this approach. At present, high-density FRAM development is focused on bit yield and bit reliability issues.
In the future, embedded FRAM has the potential to provide high-speed, nonvolatile memory functionality to logic circuits, effectively replacing embedded DRAM, embedded flash and slow SRAM. For the OEM, embedded FRAM-based SoC devices may provide a cost-effective, reconfigurable platform.
Since FRAM can serve as either data or program memory, multiple device features can be implemented using a single hardware design. The consumer will reap the benefits of FRAM in the form of small, low-cost, reprogrammable mobile Internet products.