Colorado Springs, Colo. - A chip that integrates T1 and E1 time-division multiplexed traffic over a 100-Mbit Ethernet packet link is being sampled by Redux Communications Ltd.
The Israel-based fabless provider of networking semiconductors demonstrated its RS-160 chip in June at the Metro Ethernet Forum at Supercomm 2003. In the demonstration, "pseudo-wire" T1 functions were sent to a Cisco Systems Inc. E-Line system.
Redux's initial products-such as the RS-100, launched in 2002-implemented generic network-processing functions, said Daniel Bar-Lev, vice president of sales and marketing, but the company expects more interesting opportunities in special-purpose coprocessors and has developed drop-in bridge and bandwidth-allocator chips for customer-premises equipment.
The focus on customer premises also applies to the new RS-160. While some Sonet chip specialists have combined Ethernet and time-division multiplexed (TDM) aggregation functions in chip sets, Bar-Lev said most of those devices are meant for central-office or metropolitan-edge applications and end up in equipment used by service providers. Redux is concentrating on melding TDM traffic into high-level data link control (HDLC) channels within the customer premises, creating virtual pipes for circuit emulation within enterprise routers and gateways.
Redux uses its own packet-header structure for TDM data: Circuit Emulation Service over IP, which the company has proposed to the Internet Engineering Task Force as a standard. The task force's Pseudo-Wire Emulation Edge-to-Edge working group is studying a draft of the method.
The RS-160 does not rely solely on efficiently creating packet-tunneling functions for TDM traffic. It also has an on-chip clock and data recovery device for in-band clock recovery, said Uri Rotshtein, director of research at Redux. The chip can send clock information across the network, providing Stratum-4 clock-equivalent accuracy over Ethernet networks. Jitter is 50 parts per million for a 2.048-Mbit/second E1 clock and 35 ppm for a 1.544-Mbit/s T1 clock.
The RS-160 also has its own hardwired CPU on board to manage clock recovery and to packetize and depacketize TDM information. Up to 96 Mbits/s of Ethernet traffic can be carried in the packet stream along with prioritized T1 and E1 data. Two full media-access controllers are on the chip, supporting 10-Mbit and 100-Mbit Ethernet with virtual-LAN tagging support.
Redux is supplying an RS-160 development board as a design aid, incorporating interfaces for dual Ethernet lines and a T1 or E1 connection. The board measures 60 x 80 mm and requires a 5-volt supply. Standalone RS-160 chips are offered in a 240-pin quad flat pack or 228-pin ball-grid-array package.
Redux (Modi'in, Israel) said it will offer an enhanced version of the RS-160 by this fall that supports point-to-multipoint traffic, fractional T1 and multiple E1/T1 channels.
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