San Mateo, Calif. - The PCI Special Interest Group has completed a specification for chips that will bridge today's PCI/PCI-X buses with tomorrow's PCI Express interconnect. Chips implementing the bridge are expected to emerge early next year, paving the way for systems that use both the new and old interconnects.
Intel Corp. spearheaded the design of PCI Express, a multichannel 2.5-Gbit/second serial interconnect that the company will aggressively roll into its notebook, desktop and server chip sets starting in 2004. Manufacturers of PCs and of embedded systems and cards welcomed the bridge standard, titled the PCI Express to PCI/PCI-X Bridge Specification revision 1.0, as a route to extend support to a broad world of existing cards.
System makers are expected to use the bridge in some servers and high-end desktops so that systems based on PCI Express chip sets can also provide PCI or PCI-X slots, or both. Card makers are expected to use the bridge chips as a quick way to create PCI Express cards without updating their existing ASICs.
Intel is pressing for a rapid adoption of Express, which it believes ultimately will reduce the number of chips in PC and other designs by collapsing I/O fan-out into a memory controller. OEMs and users want to protect their investment in adapter cards and not jump to a new interface for which cards are relatively scarce and expensive.
"This bridge will help enable the transition from parallel [PCI] to packetized [Express] interfaces. There's a lot of help for time-to-market and risk mitigation here," said Ted Willke, an Intel chip set designer who acted as technical editor of the bridge spec. The spec has been relatively stable for most of the year. "We have been reviewing release candidates for a 1.0 version of the spec since February," said Willke.
"There has been a little nervousness about the transition, so it's a good thing the bridge spec is out there," said Michael Krause, interconnect specialist at Hewlett-Packard Co.
Krause said he expects to see first-generation bridge chips early next year, supporting PCI-X 1.0 links at up to 133 MHz and using primarily a store-and-forward data transfer method that requires significant buffering. A second generation, coming later next year, could support PCI-X 2.0 at speeds of up to 266 MHz and provide more of a cut-through model of passing data without much manipulation or buffering.
The PCI-X 2.0 spec is itself relatively new, enabling 266-MHz and 533-MHz data rates. The first PCI-X 2.0 compliance workshop is slated for August, offering vendors a chance to try out their prototype 266-MHz designs.
Designers have several options for their bridge implementations, including how much buffering they offer, the number of secondary PCI/PCI-X interfaces they support and the extent to which they support new PCI Express error-reporting and-handling features, said Willke. Some designers have showed interest in bridges implementing multiple virtual Express channels for embedded systems.
"I would expect a wide variety of products. We made the spec highly scalable so developers could make trade-offs in cost and complexity," he added.
Die sizes, and thus costs, of the bridge chips could also vary greatly. HP's Krause said he expects some bridges will cost less than $20.
Contributors to the spec included Agere Systems, AMD, Dell, HP, IBM, Intel, Microsoft, NEC, Nvidia, Sun Microsystems and Texas Instruments. Of those, Intel, NEC, PLX and TI are expected to become bridge chip suppliers.
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