components using RapidIO earlier this year.
Kumar said Intel will leapfrog its competitors quickly because it is committed to shipping the baseline PCI Express interconnect on all new PC chip sets starting in 2004."That represents some 200 million ports doubling every year for the next two years. That alone dictates the costs for AS will go rapidly down," said Kumar.
AS is a new protocol for handling peer-to-peer packet data riding on top of the physical layer specification of PCI Express. Both RapidIO and HyperTransport recently made announcements about enhancement to their protocols for handling packets in control and data plane operations in comms gear.
To date, only the AS spec has been written in a way to take into account use in a backplane. For example, AS supports 2- Kbyte packet sizes while HyperTransport handles 256-byte and RapidIO 64-byte packets. And AS accommodates up to 256 outstanding transactions, while HyperTransport and RapidIO handle 32 outstanding transactions, said Kumar. AS also supports path-based routing for security or fail over mechanisms, as well as both credit- and status-based flow control mechanisms, he added.
Kumar said some makers 3G cellular basestations and IP-based DSL access multiplexers are already deciding to use AS. Huawei is behind the concept because, unlike its rival Cisco Systems, the China-based telecom OEM lacks a large installed base of line cards with legacy interconnects it needs to support, he added.
Agere, Intel and Vitesse will collaborate on a demo of a pre-silicon simulation of AS during the keynote address of Intel communications group CTO Eric Mentzer at the Communications Design Conference here on Tuesday when the AS spec is formally announced.
"We believe there is a market for AS, and by introducing a standard we believe that market will expand," said Kumar.