MANHASSET, N.Y. Altera Corp. will extend its push in standard products to the data-communications market with ICs that combine programmable logic with transceivers and clock data recovery (CDR) channels that pump 1.25 Gbits/second.
High-speed transceivers are a fertile field for design, ranging from Altera's programmable parts to pure speed demons attacking the 10-Gbit/s-and-beyond realm. Standing-room-only crowds jammed sessions on high-speed transceivers at the recent International Solid-State Circuits Conference in San Francisco. And several startups, including Accelerant Networks, are attacking the market for OC-192 and higher speeds.
John Daane, Altera's new chief executive officer, said the Mercury line of application-specific standard products (ASSPs) follows in the steps of the Excalibur family of programmable-logic devices with on-board microprocessor cores.
The Mercury design was particularly challenging, the company said, because the analog serialize-deserialize (Serdes) and CDR functions are sensitive to the noise generated by switching logic circuits.
"What we are now doing are analog structures that have been done in gallium arsenide, bipolar, or more recently, CMOS. Integrating that onto a PLD [programmable logic device] makes a lot of sense, but it is extremely difficult to do a CDR in CMOS," Daane said.
With a PLD block nearby, the noise issue becomes particularly complex. "You don't know what the user is going to do on the PLD portion. Because the design is unconstrained, and we don't know how many signals are going to be switching, we can't control the noise," said Tim Colleran, vice president of product marketing at Altera (San Jose, Calif.).
Mercury will ship in two configurations. The first part supports eight Tx-CDR channels, up to 4,800 PLD logic elements (the equivalent of 120,000 gates) and 48 kbits of RAM. That part is expected to cost about $150 by the end of this year in volume shipments. The larger Mercury part supports 18 channels, 14,400 logic elements and 112 kbits of RAM and is expected to cost about $350 per unit by year-end, Daane said.
The Altera road map calls for Mercury to reach 3.125-Gbit/s channel speeds by 2002, fast enough to support Gigabit Ethernet data transfers and the associated protocol handling. By 2003, Mercury channels will accommodate up to 10 Gbits/s.
The programmable logic will provide a base for intellectual-property functional blocks, including byte, bit and frame alignment, packet recovery, Sonet scrambling and other so-called soft-IP cores. While some customers will choose to implement standard protocols such as Sonet, RapidIO, Gigabit Ethernet, Fibre Channel or IEEE 1394, the company expects others will choose proprietary encode-decode and scrambling implementations.
Fewer chips, less power
Traditionally, system vendors have used a PCI bus to connect a standalone ASSP Serdes clock data recovery chip with a PLD often used for bus control logic. Another ASSP would be used to take the signals out to the line side of the application.
But as the backplane has moved to multiple serial channels at higher frequencies, Altera claims that many customers want to integrate the Serdes and PLD functions, gaining improvements in power, performance and board space.
Daane said he was pleased that Altera was able to pull off the design without resorting to an expensive acquisition.
Altera has worked with several large communications companies as initial customers. Colleran said first samples which he said were fully finished devices went out to distribution channels in February. Commercial shipments begin later this quarter, starting with an 0.18-micron, aluminum interconnect process at foundry partner Taiwan Semiconductor Manufacturing Corp.
Daane said "the vast majority" of the Mercury devices to ship this year will be manufactured on a 0.15-micron, eight-layer copper process. The core runs at 1.8 volts, while the I/O circuits function at 3.3 or 2.5 V.
The logic elements on the Mercury devices are large enough to permit Altera's proprietary Nion processor core to be implemented in the programmable-logic array. The Nion core will be able to provide a 16 x 16 multiplier function with few interrupts, for example. Or, as many as ninety 8 x 8 multiplier cores can be distributed throughout the PLD array as needed. That will be particularly helpful for wireless applications where DSP functions are needed, Colleran said.
Also, the Mercury devices support higher-bandwidth memories, including zero bus turnaround SRAMs and double-data-rate devices.
While the current family of Mercury devices does not accommodate the MIPS and ARM members of the Excalibur line, Daane said that at some point those more complex processor cores could be married with a high-bandwidth Serdes or CDR core and a PLD block.
As the industry moves to low-voltage differential signaling, Colleran said, "We give the customers a choice. They can move to differential signaling once LVDS runs out of steam, which is roughly at the 250-MHz point for LVTTL [low-voltage transistor-to-transistor logic]. With LVDS, Mercury can handle 840 Mbits/s over two pins."
At the higher signaling rates, embedding the clock with the data has significant advantages. Rather than send parallel clock and data signals, with the attendant danger of the clock getting out of phase with the data, Daane said, "With CDR the clock skew is minimized and frequencies can be turned way up, the trade-off being that it is a more complex design."
Accelerant tackles backplane
While Altera's programmable devices offer customers flexibility, other companies are zeroing in with parts that promise to relieve network bottlenecks at the backplane. Accelerant Networks (Beaverton, Ore.), for example, has chosen the backplane transceiver market as its target, according to chief executive officer Paul Nahi.
"The bottleneck inside the network has moved from the box-to-box pipes to the challenge of what to do with the data once it gets into your box. The bottleneck that was on the WAN has moved to the backplane," Nahi said.
While Accelerant Networks won't see its first silicon until May and won't ship commercial products until September or later, Nahi claims that his company is unique in targeting very high-performance backplanes.
He would not disclose specific performance-target numbers for the Accelerant transceivers but said, "We will be well north of 3 Gbits/s." Accelerant's products, he said, are optimized for backplane applications where the transceivers can be spaced from 1 inch to as many as 48 inches away from the control ASICs. The company's products will support dense wavelength-division multiplexed optical transmission at OC-192 and OC-768 speeds.
Bandwidth to the networking box can be added easily with more asynchronous transfer mode, Ethernet or optical ports. What is difficult, Nahi said, is handling that aggregate bandwidth on the line card, where backplane communications are proprietary point-to-point connections, with line cards handling 20 Gbits per second of data or more. At those speeds, ASICs rather than PLDs rule, and analog must be decoupled from digital circuits.
Nahi said several high-end network systems companies simply have not been able to ship their boxes because of difficulties at the backplane connection.
"What we are saying is that the backplane connection needs a dedicated part, one that can handle the unique effects of that environment where the copper traces can be at widely varying spacing. That is a very different market than the chip-to-chip transceivers, which can be an inch apart, or the board-to-board transceivers. We are focused on the backplane" and have no interest in other markets, he said.