Logicvision is working on a project that will bring on-chip test to mixed-signal designs that use analogue-to-digital converters (ADCs) in an attempt to stop the rise in test costs, particularly for complex system-on-chip (SoC) designs.
The company is currently in early testing with a group of customers to develop techniques and intellectual property (IP) to test a selection of typical converter architectures, said Rodger Sykes, vice president of marketing and business development at Logicvision.
"It is tough to have a standard solution for ADCs. We are working with two European customers and are currently at the alpha/beta evaluation phase.
"We are working with customers who have ADC designs and optimising the solution for those types of ADC."
The tool will follow on from a built-in self test product designed to test phase-locked loops and is part of a move to reduce the cost of analogue tests, which dominate the time it takes to test complex system-on-chip designs.
"The ability to perform basic analogue tests on a digital tester is very attractive. It is not intended to be a full characterisation but a go/no-go kind of test," said Sykes.
Because test circuitry is embedded on-chip, he said that it would become possible to perform tests on the same circuits at the board level to see whether they perform as expected under "dirty" conditions.
"As well as testing in clean conditions on an IC tester, with our board-level test methodology we can test in a real environment. We can pull out parameters at the board level. That can be tremendously valuable," said Sykes.
A deal struck between Agilent Technologies and Synopsys has also focused on the problem of rising test costs. The companies are to work together on developing design for test (DFT) approaches that will work better on Agilent's tester hardware.
The non-exclusive deal leaves space for either to pursue similar arrangements with other companies but neither has yet decided to launch a full partners programme.
David Hsu, director of marketing for test automation products at Synopsys, said: "This is the combination of two sides of the world to address common customer concerns."
The initial aim of the project is to build specific optimisations for the Agilent 93000 test platform into Synopsys' test generation tools, such as DFT Compiler. The aim is then to go on and address issues such as embedded test blocks and how they interact off-chip test hardware.
"We will tackle the low-hanging fruit first. Do the easier things. We'd like to take the tester attributes and place those in the design environment. Today, we do that very generically. We now aim to get more specific information," said Hsu.
As well as building closer links for research into linking design more closely with test, Mick Tegethoff, EDA and DFT marketing manager for Agilent, said: "We create a critical mass to drive standards."
Hsu illustrated once case where closer integration could pay off at the DFT level. He described a situation where a Synopsys customer initially used scan-based test throughout a design but got poor results. By mixing the scan tests with other approaches, the overall coverage was greatly improved.
"It took them a lot of iterations. If we can embed those tradeoffs and constraints in our tools, it could put an end to those iterations," said Hsu.
Tegethoff said new approaches could let existing platforms cut the cost of handling analogue tests on SoC designs.
"At the wafer sort stage, if you can pick a min, or a max or a nominal test instead of doing all of them, you can save a lot of time."
He said there is scope for tools that can help designers work out which test would work best for different types of analogue or mixed-signal block. The approach would at least isolate failed devices so that the others could go forward for more extensive testing.
"We want to go for just enough test," said Tegethoff.
Logicvision has been busily signing up tester manufacturers for its own partners programme, but currently lack Agilent. Adding Advantest this week, Logicvision boasts LTX and Teradyne among its test hardware partners.