Hardware-assisted verification and prototyping is taking a step forward at this week's DATE conference here, where Aldec, Synplicity, Ikos, Simutech and Aptix are rolling out new tools.
One of these vendors, Aldec, is claiming to pioneer new verification technology with its "incremental prototyping" approach to RTL simulation acceleration.
Synplicity is offering a single-chip version of its Certify ASIC prototyping software. Ikos is announcing a 15-million gate logic emulator that promises full visibility into internal nodes.
Simutech is teaming up with Scotland's Alba Centre to offer a remote intellectual property (IP) evaluation services, while Aptix is touting a prototyping environment for ARC-based systems-on-chip (SoCs).
Aldec has been talking about its hardware embedded simulation (HES) technology for the last two years, and is finally shipping a product as well as setting up a new HES division. Aldec's HES acceleration environment runs software simulation first, and then incrementally "pushes" blocks into an FPGA for acceleration, with event-by-event communications between software and hardware-assisted simulation.
Bob Fess, product marketing manager for Aldec's new HES business unit, described the accelerator as a "very friendly environment" that allows users to speed up simulators they're already familiar with. In addition to Aldec's Active-HDL, the HES accelerator works with simulators from Model Technology, Cadence, and Synopsys, leveraging the Verilog programming language interface (PLI) and VHDL foreign language interface (FLI).
The HES unit consists of a single board that incorporates a Xilinx XCV2000 FPGA, which has a maximum capacity of two million FPGA gates. Support for the 6-million gate Xilinx XCV6000 is expected soon. A software Design Verification Manager (DVM) manages the software simulation, and maps blocks into the FPGA when they're ready for acceleration.
Stanley Hyduke, Aldec president and CEO, said that the HES can provide an eight to 500-fold speedup over third-party software simulators. The speedup is up to a thousand-fold for Aldec's own simulator, he said, because the HES avoids the overhead incurred by PLI and FLI.
The speedup, Hyduke explained, depends on the kind of design, and is most pronounced for IP blocks that have a lot of transitions, such as filters.
HES users will typically run software simulation on all blocks first, and then push blocks into the FPGA when the internal debugging of the block is complete. With software simulation, users can look at any internal signals; once the block is in hardware, users can look at selected signals, but they have to add test points to their HDL code.
"For precision analysis, they use the HDL, and for speed they use the HES. They can swap back and forth," said Hyduke.
Although the DVM maps netlists into the FPGA, it's "not exactly emulation," Hyduke said. "We operate on an event-by-event basis between hardware and software. Emulators operate on blocks of data," he said. Right now, Hyduke noted, the user decides which blocks get mapped into FPGAs, and when. But he said that Aldec is working on software that will make recommendations and automatically pre-load blocks.
In addition to the FPGA, the HES hardware includes a daughterboard that can house ASICs, memories and processors. Agilent, an early HES customer, is using HES with a daughterboard to run hardware-software co-verification, Hyduke said.
At present, users can download software into memories on the daughterboard. In the future, he said, Aldec will work with embedded system providers to provide a more complete co-verification environment for software and hardware.
Aldec's DVM software only maps netlists into a single FPGA. For multiple-FPGA partitioning, Hyduke said, Aldec will support Synplicity's Certify product.
At DATE, Synplicity decided to launch a single-chip version of Certify — the regular version maps designs across multiple target FPGAs -- but has added support for design elements that should make it easier to map ASIC-oriented designs onto FPGAs for debug purposes.
Certify SC maps a netlist into a Xilinx or Altera FPGA for prototyping. Brian Caslis, director of product marketing for Certify, said the new features in the single-chip tool have yet to be added to the multi-chip Certify product.
Synplicity has taken a similar approach to Adaptive Silicon in trying to map ASIC design files onto an FPGA. Like Adaptive, Synplicity has chosen to convert the DesignWare components used by Synopsys' Design Compiler synthesis tool into FPGA versions. Certify SC also maps user-defined libraries that use the .lib format.
Other features in Certify SC include pin multiplexing for probes, which lets designers multiplex probe signals into a few pins. Other Certify features carried over to the SC version include internal debug access, gated-clock conversion, and "black box" extraction of IP or memory blocks.
The gated-clock conversion analyses the source design file for gated-clock structures typically used in ASIC designs and alters it so that those structures use the clock enable mechanisms that are supported by most FPGAs. The company said this conversion is is intended to yield performance improvements in the prototype.
While other vendors are selling hardware, Simutech came to DATE not with a new hardware box but with a new service. For SoC integrators, the price is right — all costs are borne by IP providers.
Simutech last year launched its eValab product, which uses FPGA-based CoreBoards to represent individual IP blocks. That product, said Steve Glaser, Simutech vice-president of marketing, is mostly deployed at internal reuse centres of large semiconductor companies. To reach end users, Simutech is now offering to host eValab IP Services for the semiconductor vendors.
Following the successful completion of a pilot project last year, the hosting will take place at the Scottish Alba Centre. But the actual location of the machines won't concern the end user, who will access eValab services through a web portal provided by the IP supplier.
The service will let an IP user do a catalogue search, and then run a remote evaluation of the IP, assuming there's a CoreBoard for it. Users can select algorithms or data sets, or they can upload their own software to run it on the IP block. For a single IP component, said Glaser, speeds can be very fast — up to 150MHz for a DSP, for example. But with multiple IP components, speeds decline to 2 to 5MHz, because of the need to use the eValab's backplane.
Simutech is now offering setup, hosting, and profiling services to the IP vendors, who will pay for the service. Customers include Infineon, Toshiba, and Amphion (formerly Integrated Silicon Systems).
Glaser said that "private session" services are being made available now, and that public access to eValab IP Services is expected late in the second quarter.
Finally, Aptix has teamed up with ARC Cores to offer a prototyping and verification environment for ARC-based SoCs. The environment is based on Aptix' System Explorer, and it uses the See Code debugger from ARC subsidiary MetaWare.
Richard Goering is managing editor, design automation for US sister newspaper EETimes.