SAN MATEO, Calif. The perennial battle between Altera Corp. and Xilinx Inc. is taking on a new intensity as the top programmable-logic vendors compete for design wins amid a grim revenue outlook for the rest of the year.
Altera last week said its first-quarter sales were down 22 percent, to $287.4 million, from the fourth quarter of 2000. Xilinx, meanwhile, reported that revenue in its latest quarter declined 10 percent, to $407 million, from the previous quarter. Both companies foresee further drops in the 20 percent range this quarter.
Yet the pair, both based in San Jose, Calif., are steaming ahead on the technology front, racing to get new versions of their high-density product lines into the market and to build-in support for microprocessors and intellectual-property cores.
Citing a sharp slowdown in sales in North America and softening demand from abroad, Altera's chief financial officer, Nathan Sarkisian, predicted the company's sales will fall an additional 20 percent in the second quarter, even as Altera continues to contend with high inventories. "Between ourselves and our distributors, we are looking at a year of inventory," said Sarkisian.
Altera said it has imposed a hiring freeze and eliminated discretionary spending. But its legal expenses are starting to surge as the company prepares for two patent-infringement court cases involving Xilinx and another at the International Trade Commission, Sarkisian said.
At Xilinx, chief executive officer Wim Roelandts blamed the revenue drop on what he called a telecom industry "recession" in North America. Sales were up in Japan and Europe as those regions start to phase in their third-generation (3G) wireless networks, he said, though the momentum is expected to wind down this quarter.
As a result, Xilinx expects sales to dip another 15 to 25 percent this quarter as it clamps down on spending, puts new building projects on hold and tries to reduce its 206 days' worth of inventory.
Pointing to recent 3G design wins in Japan and Europe, Xilinx claims to have gained the upper hand in nabbing high-end sockets in the networking space with its Virtex product line. But Altera has vowed to be a stronger contender at the high end this year as it rolls out its newest Apex 2 product line and revamped tool suite.
Altera admittedly lost ground in high-density programmable logic devices (PLDs) last year as it struggled with inferior software development tools for its Apex line. One problem was that compile time was too slow.
"[Xilinx] clearly had a position of product leadership, not from a silicon standpoint but from a software standpoint," said Tim Colleran, Altera's vice president of marketing.
Altera has since revamped its Quartus software suite, releasing the second version in January. The company reworked the database to speed compile times, added a new placer and changed the routing algorithms for better run-times, Colleran said.
With its new tool suite stable and shipping, Altera is preparing to roll out its Apex 2, which will go up against Xilinx's recently announced Virtex 2 line. Both companies are shooting for their new products to roll this year.
As Xilinx is attempting with its Virtex 2, Altera's Apex 2 is geared for better I/O performance. The device can deliver up to 380 Gbytes/second of data coming on and off the chip from both low-voltage differential-signaling (LVDS) I/O and general-purpose I/O. "I don't think we're ever again going to hear our customers tell us that we can't get data on and off the chip fast enough," Colleran said.
Apex 2 has twice as many LVDS channels as its Apex E predecessor, with each channel running as high as 1 Gbit/s. Altera also has devised a flexible LVDS bus that runs at 624 Mbits/s. One example of how this can be used is for moving differential signals on a backplane over a wide 64-bit bus, Colleran said.
Altera has taken LVDS a step further to devise a chip-to-chip transfer capability as an alternative to clock-data recovery, which uses clock forwarding to move data between two devices. Called clock data synchronization, this intelligent I/O scheme allows one device to communicate with several other devices to create a mesh network of chips, making it possible to partition complex functions among multiple devices.
Apex 2 also has more memory options, including larger, 4-kbit dual-port memory blocks with bidirectional, independent read and write ports. For external memory, it has hooks to several types of devices, including ZBT and QDR SRAMs and double-data-rate DRAMs.
Besides matching Xilinx on the technology front, Altera is also stepping up its efforts to strengthen ties with key networking customers. In the last month, John Daane, Altera president and chief executive, said he's visited the top five suppliers of wideband-CDMA equipment to make a case for the Apex and the company's masked PLD (MPLD), Altera's high-volume answer to ASICs.
During an earnings conference call, Daane called the MPLD the "perfect product at the right time. Several customers are converting designs from our competitors to take advantage of the Apex to MPLD family."
Xilinx chief Roelandts, however, said converting FPGAs to hard-wired devices often causes timing problems. Customers are better served using high-end programmable parts in production systems, he said during a Xilinx conference call. "The myth that high-end parts are not going to be used in production is baloney," said Roelandts.
As Altera tries to give Xilinx a run for its money in the high-density space, the company claims to have taken the lead in providing embedded soft-processor cores. Since its 32-bit Nios core was introduced nine months ago, Altera says it has sold more than 1,000 development kits and has secured 300 design wins. Nios customers include Alcatel, Cisco, Ericsson, Fujitsu, Hitachi, IBM, Matsushita, Motorola, NEC, Nortel, Philips and Sony, said Daane.
Xilinx, for its part, recently announced plans to field its own embedded 32-bit soft core, called Microblaze. The company is touting its comparatively high 125-MHz operation and low gate count. A designer could conceivably put up to 100 of the cores on one FPGA, Xilinx said.
"We think we've reached the point where we'll get these soft processors into the mainstream," said Richard Sevcik, senior vice president of software and cores for Xilinx.
Hard microprocessor cores are also on both companies' agendas. Altera said it will ship starting this quarter its EPXA10 device, with an ARM9. Customers can integrate peripherals into the programmable-logic array using the Amba bus without having to pay royalties to ARM Ltd., Altera said.
Last year, Xilinx cut a deal with IBM Corp. to integrate the PowerPC and related on-chip bus on the Virtex 2. Designed for high-speed packet routing, the PowerPC core will provide 6 Gbytes/s of I/O bandwidth, said Sevcik.
Altera too is trying to obtain a PowerPC core. The company has been in licensing negotiations with Motorola Inc. since last year, but has yet to close a deal. Altera said the talks are still ongoing, and that an agreement should be made by the second half of this year. "We're essentially good to go; it's just that there are some implementation details," Colleran said.