LONDON Two startups, one in the United States and the other in the United Kingdom, expect to bring clockless processor-based system-on-chips to market next year or soon after.
Two-year-old Asynchronous Digital Design Inc. in the United States is flush with $16 million from a recent investment round, while U.K.-based Self-Timed Solutions Ltd. comprises a team of university researchers still working on their business plan and a pitch for venture capitalists.
Asynchronous Digital Design (ADD), based in Pasadena, Calif., was spun out of the California Institute of Technology in January 2000. In the U.K., the Self-Timed Solutions team, under Steve Furber, a professor of computer engineering at the University of Manchester, is preparing a business plan, although a company has not yet been formed.
In a familiar tale of transatlantic technology differences, the U.S. offerings are likely to be MIPS-architecture-based and aimed at high-speed data, while the U.K. group is experienced in the design of asynchronous versions of the ARM architecture of ARM Holdings plc (Cambridge, England) and is looking at smart cards.
After a couple of false starts during the 1990s, commercial activity is again building in the area of self-timed or clockless logic. Besides these startups, another company, Theseus Logic Inc., is working with Motorola. In addition, Intel, Philips Semiconductors and Sun Microsystems are all experienced in asynchronous circuit techniques.
Asynchronous logic does away with the clock signals that conventional logic uses to control circuit activity. Instead it uses logic modules that are self-timed and that pass results among one another using handshaking protocols.
Not using a clock signal saves power and the approach can improve the radio frequency noise characteristics of chips compared with their clocked equivalents, according to its adherents. And because circuits are data driven when there is no data present, there is no activity, providing a further power saving. But standing against the technique are problems testing and debugging circuits and integrating them with conventional clocked circuitry.
Roots at Caltech
Two months ago ADD closed a funding round that raised $16 million. It has technology, a patent portfolio and an EDA tool chain for asynchronous design that has come from the computer science department at Caltech.
ADD was founded by Andrew Lines, chief technology officer, and Uri Cummings, vice president of engineering, who has studied under Alain Martin at Caltech. As part of a renewed commercial push that will use the $16 million, the company has just brought in Bob Nunn from Vitesse Semiconductor Corp. as chief executive officer.
"The first year was really an extension of university activity," said Mike Zeile, ADD's vice president of marketing. Zeile said ADD has two 32-bit processors implemented in an asynchronous design style.
"We have the Vortex CPU. It's running quite nicely in the high millions of transitions per second. We've also got lots of experience with MIPS cores. I think MIPS is more likely for an exposed target but we might use Vortex for very deeply embedded applications," Zeile said. As well as running asynchronously and quickly, the proprietary Vortex architecture allows up to 14 instructions to execute in parallel.
Current MIPS and Vortex processors from ADD are being aimed at standard CMOS processes such as a 0.18-micron CMOS process from United Microelectronics Corp. and a 0.15-micron CMOS from Taiwan Semiconductor Manufacturing Co.
Zeile said that the full MIPS implementation was compatible with the MIPS32 instruction set but that the company does not yet have a formal licensing agreement with MIPS Technologies Inc. (Mountain View, Calif.).
Zeile said that ADD processors have consistently shown better performance in a given process technology and lower power consumption than clocked devices. "Our MiniMIPS processor went at [the equivalent of] 250 MHz in 0.6 micron. That was twice as fast as anything else on that process. And there's 30 percent less circuitry and therefore 30 percent less power consumption, just because we don't have to do clock distribution."
But Zeile said that the company would not simply try to market asynchronous processor cores. "We're in the business of delivering silicon; chips that solve customers' problems. So I expect it to be a mix of software-on-CPU and hardware. Almost everything we've done has had some hard-wired element."
Zeile added, "We're looking at wireline applications in general. Network processors is one area we're looking at. The performance required is at gigabits per second and multigigabit-per-second rates. Our technology does a great job at those data rates."
However, one of the biggest advantages for self-timed circuitry is that it could avoid one of the biggest problems with deep-sub-micron design, which is getting the synthesis of logic to converge with detailed layout and its effect on the timing implications of the manufacturing process technology.
For deep-submicron clocked circuits this has become an iterative problem known as "timing closure." The finer the process geometry, the harder it is becoming.
"We let asynchronous blocks be freely dropped side by side in a hierarchical fashion," Zeile said. "And because they free-run and pass on results when they are available, timing closure is less of a problem. So one benefit could be time-to-market."
ADD is not predicting just when its product will appear on the market. Zeile said 2002 would be a year of engineering development and engagement with early customers. But he said that by 2003 he expected ADD to have launched a system-level chip based on asynchronous circuitry.
Next year should also see the formation of a similar U.K. company with its own academic pedigree in asynchronous logic, but focused around the ARM architecture.
"Self-Timed Solutions Ltd. is something we are trying to start up as a spinout from our group at the university," Furber of Manchester University said.
Furber has been guiding asynchronous logic research during the 1990s. He was one of the architects of the Acorn RISC Machine, which eventually became the ARM 32-bit RISC processor.
His group's clockless version of the ARM is known as Amulet and the latest version implements version 4T of the ARM instruction set architecture.
One area the Amulet group at Manchester has started investigating is smart cards. The group is taking part in a European collaborative research program called G3card, which is looking at the benefits of asynchronous logic in smart cards.
"It's clear that commercial companies are getting very worried about smart-card security and that asynchronous logic could make a contribution there, Furber said. "However, how much people will pay for extra security is not clear. The smart-card market is very price-sensitive.
"But we are not starting a company until we are sure there is a market," Furber said. "Asynchronous logic has a history of being a hard sell. We have to find the right match [to our technology] but if we can I don't think raising the money would be a problem."
Furber said that he would not be leaving Manchester University but he could be involved with the spin-off during its startup phase.
The embryonic company has several university-developed circuits that it wants to take to market. These include the most recently developed ARM-compatible clockless 32-bit RISC called Amulet3; a self-timed Viterbi decoder; and a configurable, multi-issue digital signal processing core .
A team of researchers that includes Steve Temple, a research fellow at Manchester University since 1993, is "ready to go" when due diligence is completed.
Under an earlier intellectual-property agreement, ARM has the rights to the university's asynchronous logic implementations of the ARM architecture.
"They've [ARM] been quite straightforward with us," Temple said. "They'll allow us to buy a license to manufacture Amulet-based chips just as they would any other group. And if we succeed they will get royalties.
"We are talking to companies large and small and we have a large team waiting to go," he added. Temple said that he expects Self-Timed Solutions will have been formed by mid-2002.
Both groups have difficult educational work ahead, according to technology analyst Jim Turley.
"The advantage of asynchronous logic is meant to be low power, and at very low speeds it does have an advantage. I can see why you might go after smart-card applications. It's also true that for streaming data applications there are major periods of dead time, and no data means no electricity. But you need EDA tools and you can't do debug, and just integrating with conventional logic is difficult.
"I'll applaud from the sidelines but I don't see any quantum improvements arising from asynchronous logic," Turley said.
When asked why Self-Timed Solutions had more chance of success in asynchronous logic than previous attempts, Furber said, "The technology is more developed. We have solved more of the problems and we have got EDA tools. We've got an effective high-level synthesis tool called Balsa. Marble is our on-chip low-energy bus technology, and Chain is our self-timed chip-area interconnect system."
And Temple reckons that the group at Manchester has made headway on the testing problem.
"We don't necessarily have a good handle on [test] coverage but we have techniques, such as injecting code into the processor while it's on the tester, that help produce a pass/fail signal. Because the processors are asynchronous, once the code is in there it just runs. This has been very fruitful and we usually configure it to just produce the ASCII word "YES" at the end. If it does that, the processor has passed."
The next test for asynchronous logic is the test of the market. At least in one sense for ADD and Self-Timed Solutions the clock is ticking.