SAN FRANCISCO Synthesized Logic LLC, a two-man outfit, has developed a synthesizable soft core that's compatible with the ARMv4 processor and is ready to license it to interested parties. The core does not violate the patents of ARM Ltd., the startup's founders said.
Synthesized Logic is talking to chip and systems companies about its RTL implementation of the core, which was designed to avoid infringing on any patented technology.
"This is a clean implementation and it includes no trade secrets from ARM Ltd.," said Jeff Mock, co-founder and chief technology officer of Synthesized Logic, based in San Francisco. The core is target at wireless, portable, communications and low-power applications, Mock told EE Times.
Aware of litigation that ARM Ltd. has pursued against other companies that have tried to market ARM-compatible cores, Mock said he looked at ARM's patents along with co-founder Marlin Gilbert and a patent attorney to make sure patents were not violated. Mock worked with Gilbert, who is president and chief executive of Synthesized Logic, at Silicon Graphics Inc. in the 1980s.
"I think what we've done is on the up-and-up and we've been careful not to violate their patents," Mock said.
The company's processor core can run the ARMv4 instruction set and leverage the tools that support the ARMV4 architecture.
The core is unique in its ability to synthesize well for both FPGAs and ASICs, the founders said. This way, engineers can use an FPGA to build a prototype and products and get to market two to three months faster than if they used an ASIC-based prototype, Mock said. The core has greater configuration flexibility and will be cheaper than ARM Ltd.'s core, he said.
FPGA-based prototypes are an important new area for embedded processor development, Mock said, given the improved performance and tool efficiency of FPGAs. The Synthesized Logic core will be a good fit for system-on-chip designs and could serve as a central processing unit in personal digital assistants, he said.
Licensors of the Synthesized Logic core will receive the RTL (register transfer level) implementation and an evaluation platform, which uses a Vertex FPGA from Xilinx Inc. and runs the ECOS operating system of Red Hat Inc.