SAN JOSE, Calif. Leading FPGA vendors are looking at ways to put multiple 3.125-Gbit/second transceivers on the edge of their products and to persuade designers they no longer need separate application-specific standard products for the job.
So far, Lattice Semiconductor Corp. and Xilinx Inc. have announced they are shipping products with these high-speed serial links on board. But they won't be alone: Actel, Altera and QuickLogic promise to soon wrap these fast serial I/Os around their own field-programmable gate array fabrics.
Many of the resulting FPGAs will embrace some of the most common encoding and scrambling schemes in hardwired ASIC gates while leaving higher-level functions, such as the link layer, up to designers to program into logic gates. Beyond that, FPGA vendors are taking different paths when it comes to the type of programmable-logic fabric and processor configurations they will support.
What's fueling these high-speed I/O ambitions is that backplanes, disk drives and box-to-box system links are all moving toward high-speed serial links that incorporate clock-data recovery (CDR), in which the clock is embedded within the signal. The alternative is to keep using wider parallel signal paths and an external clock, but most say that keeping so many signals in synch by this method is becoming untenable as signals surpass 1 Gbit/s. Gigabit Ethernet, Rapid I/O, 3GIO, PL-5, Xaui and other interfaces rely on CDR in some form, and FPGA vendors hope to cash in on the trend by promising to support as many of these interfaces as they can with standard products.
Finding ways to support new I/O schemes is familiar territory for FPGA vendors, but CDR technology is new to most. Only recently have vendors of application-specific standard products tackled the finer points of the high-speed serial I/O in CMOS.
"Two years ago, it was only available in gallium arsenide as discrete chips, and those would consume two and a half watts," said Erich Goetting, vice president and general manager of the Advanced Products Group at Xilinx Inc.
Meshing the clock and data and pushing it over a pair of wires is not trivial for those designing the serializer/deserializer (serdes) devices. The traces become so crammed with signal that the intervals between clock and data are measured in picoseconds, requiring special encoding or scrambling schemes to keep them at regular intervals, Goetting said.
This takes more analog expertise than most FPGA vendors can muster, so many are looking for outside help. Xilinx tapped Mindspeed Technologies for the SkyRail transceiver technology used in the Virtex-II Pro. Actel Corp. is working with design-services specialist Tality Corp. for its 3.125-Gbit/s capability, said Actel chief executive officer John East. Altera Corp. has its own team familiar with CDR, yet is seeking help from an undisclosed partner for the 3.125-Gbit/s I/O that will be bolted onto future products. And Lattice Semiconductor, which has had its eye on expanding beyond complex PLDs for years, recently bought from Agere Systems the Orca FPGA product line, which came equipped with multiple 3.125-Gbit/s interfaces.
Lattice president Steven Laub said his company intends to give Orca the marketing focus it deserves but lacked when it was part of Lucent and its spin-off Agere. The ORT82G5 which can support eight 3.125-Gbit/s serdes channels has just started to move into volume production.
Probably the most ambitious FPGA with high-speed serial links is Xilinx's latest Virtex-II Pro family, which can hold up to 16 transceivers running at 3.125 Gbits/s each and as many as four PowerPC 405 CPU cores "immersed" within the die.
Not to be outdone, Altera said it is hatching plans to field its own FPGA that can run at 3.125-Gbit/s I/O capability. Though mum on specifics, Altera said the device will be based on its forthcoming Stratix architecture. The company got the ball rolling last year with its 1.25-Gbit/s Mercury serial transceiver line, which Altera says is now in the hands of hundreds of customers.
SRAM gates debated
Lattice, Xilinx and Altera are placing their serial I/O blocks around SRAM-based FPGA gates that can be reprogrammed, but other players are preparing one-time-programmable devices with high-speed serial links. These latter companies tout higher logic speed, lower power consumption and higher reliability than SRAM-based parts. One is Actel, whose upcoming BridgeFPGA family will combine the company's anti-fuse programmable-logic fabric with a low-voltage, differential-signaling physical layer running at 3.125 Gbits/s, topped with hardwired ASIC gates that act as programmable protocol controllers. "We're finding that there is a big anti-SRAM market," said East.
Similarly, QuickLogic Corp. expects to unveil by the end of the second quarter a device with 3.125-Gbit/s I/O wrapped around its amorphous-silicon-based FPGA fabric, said president and chief executive officer Tom Hart. Hart said the company's FPGA technology is "superior along almost any dimension than SRAM technology, including performance, die size, power dissipation and ease of pin locking."
The earliest products out of Lattice and Xilinx are indicative of what to expect. Both companies pack as much functionality into hardwired ASIC gates as they can, to optimize area and power efficiency. This include features like native 8-bit/10-bit encoding and the ability to aggregate multiple I/O channels, known as "channel bonding" or "multichannel alignment."
Lattice and Xilinx are also eyeing scrambling techniques as an alternative to 8-bit/10-bit encoding to curry favor with Sonet equipment makers. Xilinx's Virtex-II Pro can bypass 8-bit/10-bit encoding and implement a scrambling algorithm that users program into the FPGA, which usually requires less than 1,000 gates, said Goetting. Lattice expects to have a device that supports Sonet scrambling and framing within a year, said Steve Stark, director of product marketing at Lattice.
Many see implementing the high-level networking protocol stacks in software as a must. The Infiniband spec, for example, requires 300,000 gates to implement without a processor vs. 25,000 gates with one, said Goetting. FPGAs are going to need some way to link with CPUs for these functions, but there's some debate over whether the CPU should be embedded in the FPGA or left as a separate device.
So confident was Xilinx that an embedded CPU was the way to go, it came up with a special way to immerse the first four metal layers of a PowerPC 405 and have five more interconnect layers running over the top.
But Altera, which has an embedded ARM9 core in its Excalibur product line, believes the technique will prove too costly and doesn't give designers a choice about what CPU to use. Moreover, the company says, the PowerPC 405 in Xilinx's products lacks the processing power for high-speed backplanes.
"Having separate functions for a processor and separate functions for the high-speed serial I/O is the better way to go," said Tim Colleran, Altera's vice president of product marketing.
Xilinx countered that fusing the CPU to the FPGA fabric and exploiting the 64-bit bus interfaces of the 32-bit PowerPC 405 eliminates performance issues. "There's no comparison between a standalone processor and one that's immersed in an FPGA," said Kent Dahlgren, a member of the technical marketing staff. "The bandwidth we have is far more important than [CPU] Mips or megahertz."