As the speed of modern high-performance buses increases to 400 MHz and beyond, signal integrity concerns have a large and increasing effect on timing closure. Unfortunately, these high-speed chip-to-chip interfaces, with their extremely fast edge rates and small timing margins, exceed the capabilities of standard board-level interconnect characterization techniques. A new approach, I/O buffer-based timing, provides a better approach to board-level timing closure.
The figure below shows a system simulation that we did for one of our clients. The plots show data switching at the receiver with multiple simultaneously switching aggressor signals nearby. The driving buffer is excited by a 127 bit pseudorandom bit sequence. The jitter plot at the top shows timing based on the standard pin-to-pin board-level approach.
Figure 1 -- I/O buffer timing example
If we were to use this simulation for jitter measurements and to calculate our timing, we would badly underestimate the actual timing push-out at the die itself. The plot at the bottom of the figure shows the jitter when package effects are included. This jitter, created by data pattern dependant cross-talk within the package, is many times that of the board-level system and is the dominant signal integrity issue in this design.
The manufacturer's specifications may keep you from trouble cases like this, but there is no way to know for certain, given how most devices are specified. I/O buffer based timing is clearly a better choice because it measures timing where it matters, at the die.
Many of the details of system performance that have been ignored in the past are now dominant performance-limiting matters, with the integrated circuit package probably the worst offender. IC manufacturers' timing specifications generally do not account for the timing push-out, which is caused by the signal integrity effects of the package. In addition to the package effects, device data sheet timing information is often arbitrary and ill defined, leaving the system designer guessing at worst-case timing conditions.
At best, using standard methods, accounting for these effects will require overly conservative system design to ensure correct operation across the entire range of operating conditions. This will leave timing margin and money on the table. Worse, failure to account for these effects may cause system failure because of uncharacterized timing margin failures. Omissions of these effects are most often the smoking guns behind the wide range of well-publicized component and system failures seen in recent history. It is important to understand why the standard method fails muster.
Timing specifications at the pins or pads of a device, combined with board-level electromagnetic simulation of flight time, cross-talk, jitter and skew, are the principal tools used to compute timing margin. If the signal integrity engineer works carefully, the electromagnetic effects of the board-level interconnect can be well characterized by one of a number of good board-level signal integrity tools now available. However, device timing specifications are another matter.
A survey of device data sheets will show that there are few true standards for specifying device timing. Worst-case timing is generally presented, but usually little or no information is provided about the conditions under which that timing is guaranteed. Loading conditions are often arbitrary and frequently unlike the environment in which the device will actually operate. The designer is often left guessing about the conditions that bring about the worst-case timing, such as temperature, process variation, data patterns and simultaneous switching outputs, and whether it really is worst case. To complicate matters more, most of the package effects are left vague or unaccounted for.
A typical package might be a ball grid array, 35 mm square or even larger, with hundreds, or perhaps thousands, of I/Os. These packages are normally constructed as miniature printed-circuit boards, with many fine-pitch closely spaced conductors that are often quite long, up to 20 mm, connecting die pads to package balls.
When a signal leaves the driving buffer, the edge rate is as fast as it is going to be; from an interconnect point of view the signal is in its most demanding state. The first structure that the signal encounters is the IC package. Signal flight time along these conductors, within the package, is on the order of rise time for modern bus speeds, about 100 ps to 200 ps. Thus, the package is potentially the source of very significant crosstalk, ringing, skew and impedance mismatches. In addition to these effects, the package has potential impact on I/O buffer performance in the form of switching threshold shifts and gate modulation due to power rail droop.
Board-level timing closure for modern high-performance systems demands a more sophisticated approach to timing analysis than is generally used. Accurate timing calculations based on pin-to-pin timing specifications are difficult or impossible because the specifications are not well defined for the task and worse, often ignore the significant effects of the package.
If we acknowledge that this pin-centric methodology drives much of the inaccuracy in our timing calculations, it makes sense to move the starting point for our simulation work to the I/O buffer itself. This is where timing closure must be achieved, not at the pin. This approach is now being utilized by some of the leading companies and experts in the industry. We call this method "I/O buffer based timing." The benefits can be dramatic.
For this approach to work, designers must have access to accurate models for the device package, from the die to the pc board pad and, at a minimum, a good behavioral model for the buffer itself. Timing should be specified at the output of the buffer, not the device pin.
For even higher fidelity, the simulation reference points can be moved to the input of the output buffer and the output of the input buffer. The advantage of this approach is the accurate modeling of power supply effects on the buffer, thus increasing the accuracy of timing calculations. This, of course, requires a good package model for power distribution to the I/O buffer in addition to the signals. It also requires a Spice-based model for the buffer, something most vendors are understandably reluctant to release.
Successful timing closure in the face of signal integrity concerns found in modern high-performance systems will require us to improve our methodology. This must be a collective effort, combining the work of device vendors, simulation tool vendors and their customers. The ingredients for success are:
- We need standard methods for specifying worst-case timing in the context of actual device operation. The best way to do this is to define timing at the die, not at the pin. Exact methods of determining worst-case timing should be documented and available to designers.
- System designers need ready access to accurate package models that correctly account for all important effects such as crosstalk, delay, skew, return path and power delivery.
- We need accurate modeling of the I/O buffers themselves. At a minimum, this should consist of a good behavioral model that is well correlated to the manufacturer's actual Spice model for the buffer.
- We need simulation tools to bring all the pieces together.
- And finally, we need a new "standard" methodology that computes timing from die to die, rather than from pin to pin.
Changing how things are done is not easy, but system performance demands will force us to improve how we compute timing and verify system operation. As customers, we have to recognize the looming deficiency of our previous approaches to system verification. We should require that our vendors give us the tools that we need to successfully design cost-effective, robust, high-performance systems. Ultimately, this is in everyone's best interest.