Jeppe Jessen, CEO, IP Semiconductor A/S, Soeborg, Denmark, Amit Dhir, Manager, Strategic Solutions, Xilinx, Inc., San Jose, Calif.
Next generation routers are providing solutions to service providers who need to introduce new revenue generating services while ensuring service quality. Key to solving these issues for router vendors are platforms that can be quickly configured to add services at low power and cost.
System analysis indicates that the key to meeting these stringent requirements comes down to two tasks within the router. Packet classification and policing-rules management are the critical functions that define to a large extent the added value of the system. In addition, these two tasks typically consume most of the power and occupy the largest amount of board area.
Investigation of existing hardware alternatives indicated that implementation of these functions might lie within the range of leading edge FPGAs. For example, the Virtex-II Pro, combining an embedded PowerPC core with an advanced FPGA, provides a platform for flexible implementations of both the classification and policing stage. In addition, existing intellectual property developed for this device, the SPEEDRouter Network Processor core from IP Semiconductors, provides a unique platform for critical data path functions such as packet validation and classification, packet modification and packet policing
With the embedded PowerPC, the platform also provides a fully integrated control processor environment. In total this shifts the use of FPGAs from being the glue logic of the system to becoming one of the centerpieces of value creation in the design and a key element in solving the needs of the Service Providers.
Basically, the SPEEDRouter has two types of blocks: Ready For Use (RFU) blocks that do not need modification and are delivered as netlist and Verilog Shells blocks consisting of a Verilog module with well-defined interfaces, which can be used for customizing and feature implementation.
A general platform needs to support a wide range of interface standards. Designers can then reuse the same processing platform to develop code and features on multiple line card designs. The set of interface cores of the Virtex-II Pro family provides support for such interfaces as: POS-PHY L3, Utopia-2, Flexbus-3, Gigabit MAC, CSIX. In addition the Virtex-II Pro platform opens up the possibility to interface directly to in-house ASICs with proprietary interfaces.
Finally the FPGA platform provides room for added value with the design of custom hardware accelerator cores for such tasks as encryption and decryption, check-sum calculations, DSP processing and more.
The SPEEDRouter Network Processor core uses the SPEEDAnalyzer lookup engine for offloading of such computational intensive tasks as classification and policing.
Central to the SPEEDAnalyzer is the SearchVLIW microprocessor. The processor is a special purpose 64-bit VLIW microprocessor with a pipelined core operating with multiple parallel threads (lookups). Lookup speed is enhanced by special execution units such as built-in Address Resolution Logic (ARL) and special ALU instructions. The SearchVLIW interfaces to low-cost SDRAM through an intelligent multithreaded memory controller.
The SearchVLIW performs lookups, classification and policing tasks by execution of programs, which provides maximum flexibility for the designer while providing the industry's highest performance level per watt of power.
The basic architecture of the SPEEDRouter with its cut-through data path and the SPEEDAnalyzer with its support for low-power SDRAM, eliminates the need for expensive and power hungry SRAM and CAM devices. The solution consists of only one Virtex-II Pro FPGA and a SPEEDAnalyzer plus standard SDRAM. In comparison other network processor solutions rely on multiple memory interfaces with SRAM and CAM support, hence the SPEEDRouter solution can reduce power consumption and device count by more than 80% compared to standard network processor solutions.
As an example of the platform's flexibility and performance, consider the case of a full-duplex OC-48 line card supporting MPLS based VPN and traffic Policing. Such a line card can be implemented in a two stage implementation.
The first stage performs packet validation and the second stage performs ingress policing using a dual leaky bucket algorithm implemented in the SPEEDAnalyzer. The two stages can be implemented in 4 devices plus SDRAM and consumes less than 30W in total.
The new level of performance and features of recent FPGAs provides a powerful platform for building revenue-generating routers and switches. The architecture of the SPEEDRouter Network Processor core and the SPEEDAnalyzer lookup co-processor provides a platform with room for a high degree of added value. The interfaces cores available for Virtex-II, the fully programmable SPEEDAnalyzer lookup engine, the embedded PowerPC for control plane functions, and the well-known tool flow of both FPGA and PowerPC embedded software design provides a highly flexible platform. The solution provides 5 times improvement in power and device count as compared to competing solutions and at the same time delivers a new level of performance.