Editor's Note: In Part 3 of this series, consultant and ASIC designer Tom Moxon covered several RTL and logic synthesis design flows. In this installment of the series, he'll describe new physical optimization and layout design flows, and will discuss signal integrity issues and show how they are currently being addressed.
In the previous installment we discussed several of the choices available for RTL and logic synthesis design flows, moving from RTL to a gate level netlist representation. Most designers are now following this step with a combination of physical synthesis and heirarchical gate level placement and analysis/optimization flows that include tools like First Encounter, Physical Studio, or TeraPlace prior to detailed routing. We'll examine some of these flows in this installment.
When I first started this article series last year, Avanti, Silicon Perspective, Plato, and Simplex were independent companies, and the outlook for significant tool integration was unclear. Since that time, there has been a winnowing of the
EDA field, and it appears that the movement toward complete RTL to GDSII flows is accelerating.
Cadence Design Systems
With their recent acquisitions, Cadence Design Systems is now poised to make major improvements in their EDA tool offerings. The acquisition of CadMOS Design Technology, Silicon Perspective Corporation, Plato Design Systems, and Simplex Solutions certainly gives Cadence a boost with their current point tool offerings and sales. But more importantly, it allows them the opportunity to integrate these new acquisitions into a comprehensive, next generation, RTL to GDSII design flow based on an underlying, integrated database technology (Genesis) and a unified user interface.
Some of this work is already completed with Ambit BuildGates, and other parts are already well underway, with Silicon Perspective's First Encounter. But how long it will take to fully integrate all of the other acquisitions is anyone's guess. My prediction is that DAC 2003 will see a very different EDA landscape than what we have today.
Each of these acquisitions brings some very talented individuals and management to Cadence, as well as some distinct technology and capabilities. Silicon Perspective brings hierarchical partitioning, floorplanning, and global timing management. Plato Design brings multiprocessor and multithreaded detailed routing, while CadMOS and Simplex bring some of the best extraction and signal integrity technology in the industry. Many of the key contributors in these companies have worked at Cadence before, and are already familiar with the company organization and culture. Of course, with so many overlapping products and competing development groups, it will be a challenge for Cadence to articulate and deliver a clear roadmap for a comprehensive, new RTL to GDSII flow - but they certainly have the right people and technology to accomplish this.
SoC Encounter is the first new product to come out of the recent acquisitions, providing a hierarchical RTL to GDSII flow by integrating the First Encounter floorplanner and the Cadmos CeltIC signal-integrity analysis engine with Cadence's existing Silicon Ensemble PKS (Physically Knowledgeable Synthesis) tool. You can input a register-transfer-level or gate-level netlist to SoC Encounter, and then construct a flattened full-chip "silicon virtual prototype" that accurately represents the final chip's timing, die size, and power, including signal integrity analysis of most of the expected detailed routing.
With the Simplex Solutions
acquisition, Cadence now gets to integrate the technology behind the "three storms" -- SignalStorm SoC, VoltageStorm, and ClockStorm.
Some recent studies from Collett International and other companies indicate that over fifty percent of device failures can be attributed to slow timing paths, often caused by excessive IR drop on clock distribution buffers. Signal integrity analysis has always been important, but it is now critical to achieving first-time silicon success.
In the realm of 130nm and below, signal integrity also has as much to do with performance recovery as it does with correct device functionality. Considerable timing margin is being consumed by crosstalk, interconnect delay, and IR drop. However, one of the big problems here is that most models just don't have the accuracy required for the signal integrity analysis of sub-130nm designs.
"It's the modeling, stupid!"
The most accurate signal integrity tools all need to generate their own models due to the deficiencies in vendor supplied libraries and model formats like the .lib and the .spdm formats. For example, in .lib the voltage derating is typically specified for the entire library as a whole (where it needs to be specified on a per-cell basis), with only linear derating available (derating effects are often nonlinear). Simplex has created the .ecsm (effective current source model) format to be able to represent both driving and holding resistance accurately. This is important for modeling multi-driven nets and multi-driven meshes, and supporting the analysis of more aggressive design styles.
SignalStorm SoC provides a unified solution that integrates all delay factors with an advanced, hierarchical delay calculator that supports OLA/ALF. It can analyze performance based on instance specific IR drop effects, distributed interconnect delay effects, and crosstalk effects. SignalStorm SoC is a mature product as it is. However, I'm really looking forward to seeing this technology seamlessly integrated with SoC Encounter, as the dust settles after the Simplex acquisition.
With the acquisition of Simplex, Cadence also picks up the X-Architecture, which rotates the primary direction of the interconnect in the fourth and fifth metal layers by 45 degrees in relation to conventional orthogonal, or Manhattan, architecture. The X-Architecture has been slow to catch on in the industry, as it needs to be supported throughout the design flow and all the tools in the chain. With the acquisition of CadMOS Design Technology, Silicon Perspective Corporation, Plato Design Systems, and Simplex Solutions, Inc., Cadence can insure a seamless integration of the X-Architecture throughout their design tools.
Stabie-Soft Solutions' floorplanning and power/ground routing product, Strategy, has been used by several companies to provide the integration necessary to link First Encounter and the Nanoroute router.
I've always appreciated Stabie-Soft as an example of how one motivated engineer can produce solutions that rival the "big guys", and are quietly used to complete many designs without lots of unnecessary hype and marketing. Strategy can be used for floorplanning with a number of different tools, providing links for Incentia's DesignCraft Pro, Mentor's Teraplace and other routing systems. Stabie-Soft also provides Slam-Edit and Slam-View for layout editing and viewing/review.
Stabie-Soft Solutions - Slam View Screenshot
Stabie-Soft also provides DRC/LVS and plotting solutions that work well and are inexpensive - a rarity in the EDA world today.
Mentor Graphics Corporation
Several colleagues have reported using the Mentor Graphics physical optimization tool Teraplace successfully for post-synthesis/pre-layout optimization and planning. Mentor purchased TeraPlace several years ago from CLK CAD and then improved the tool with the addition of TeraView, an interactive graphical editing interface. TeraOptimize, their timing optimizer, and TeraCTS, a clock tree synthesis tool, round out the TeraPlace suite.
TeraPlace, originally developed by Chung-Kuan Cheng, professor of computer science and engineering at the University of California at San Diego, was previously used as the placement engine of SVR's SonIC 3.0 layout system. We'll have to see if Mentor announces any new improvements in this area, as
the Cadence SoC Encounter and Sequence Design Physical Studio are now addressing signal integrity issues as part of this flow step.
Sequence Design Inc.
Sequence Design was formed by the merger of Frequency Technology, Sente Inc. and Sapphire Design Automation. Sequence combines the extraction expertise of Frequency Technology, the power reduction technology of Sente, and the signal integrity and optimization technology of Sapphire. With their new "NanoCool Initiative", Sequence has carved out an important niche in low power/low voltage design tools, and I'm finding their products in the EDA toolboxes of several customers.
Starting with top-level RTL code(Verilog or VHDL), Power Theatre accounts for both static and dynamic power consumption by identifiying structures such as RAM, ROM, datapaths, control logic, I/O pads, and clock logic. Based on the Sente "Watt Watcher" technology, Power Theatre can analyze peak and time varying power, and "WattBot" agents can help identify power reduction opportunities. For those of you that doubt the importance of power analysis and design in the sub-130nm world, take a look at what happens when the heatsink is removed from four different microprocessors running under load at Tom's Hardware.
After Logic Synthesis, Power Theatre can be used to insert power gating logic and to plan and design the power grid for your chip. Physical Studio can then be used to perform low power clock tree synthesis.
Sequence Design Inc. - Power Theater Screenshot (Power Map)
Sequence Design Inc. - Power Theater Screenshot (Cycle Power)
After placement, Physical Studio can perform pre-route timing optimization, power distribution, and signal integrity optimization by adjusting the placement for avoidance of these problems. A common static timing analyzer (STA)
uses timing windows and dynamic coupling compensation coefficients to model cross-talk delay, glitch, and IR drop effects.
After routing, Physical Studio can perform "along the route" correction for signal integrity problems, based on a set of 3D topology transformations. Finally, Power Theatre and the ShowTime timing analyzer can be used on the completed design to perform validation of power, timing, noise and reliability requirements.
Key to the Sequence Design tools are their high accuracy and high performance extraction engines. ExtractionStage is a suite of extraction engines that all use the same process description library, known as the Interconnect Primitive Library (IPL). A full 3D field solver is used to build the IPL for each process technology, such that each physical primitive in the IPL has a complete RLC model. Sequence Design's patented "Topological Decomposition" algorithm decomposes a wire into minute primitives, and then performs a table lookup of these primitives in the IPL. The result is an extractor that has the accuracy of a full 3D field solver, but the speed and capacity necessary to be useful for a full-chip SOC design.
With many of the new, low resistance copper interconnect processes today, accurately modeling full-chip inductance (L) is critical to achieving high frequency operation. The Sequence Design extraction engines can calculate series inductance (the combination of self-inductance and mutual inductance), which is particularly important for high drive nets and meshes. High power clock distribution nets, cross chip data busses, and I/O driver nets often show large discrepancies when compared with other extraction tools that only handle distributed RC effects. When you're talking about the primary clock distribution nets, that often means the difference between a working chip and a useless lump of sand.
Pulsic has just introduced their new physical design tool Lyric, which provides a gridless routing environment for deep sub-micron IC design. The Lyric tool contains a timing driven routing engine, and a tightly coupled, high speed RC extraction engine that is used for both post-routing extraction and during routing to achieve fast timing closure. The integrated RC extraction engine is also employed to provide a set of signal integrity solutions. Lyric can address problems such as antenna damage, crosstalk and circuit stability.
Pulsic - Lyric Screenshot (Edit)
Pulsic - Lyric Screenshot (Routed)
The core team of designers from Zuken-Redac's place and route group formed Pulsic Limited and they have just released the Lyric product.
Monterey Design Systems
Several of my consulting customers are using Monterey Design Systems tools for their physical design work. They have been quite pleased with the results produced with Monterey's "Global Design Technology", which allows for the optimization of many different design parameters simultaneously.
Monterey's tools include IC Wizard, a hierarchical design planning tool; Sonar, a physical prototyping tool; and Dolphin, a complete physical design system.
IC Wizard is employed to perform automatic timing driven block placement, shaping, and port placement based upon system-level constraints and connectivity using a gate-level netlist along with any hard macros. The system constraints can be budgeted into physical and timing boundary conditions for each design block, in order to drive the cell level tools downstream in the design flow.
Automatic partitioning can be performed as part of the optimized placement and block shaping process. IC Wizard includes a global router used for congestion driven port placement, routing channel sizing, feed-through insertion, and buffer insertion. The integrated extraction engine of IC Wizard provides interconnect wire RC values based on the results obtained from the global router. An integrated Timing Engine and Delay calculator is used to budget the system timing requirements into partitioned block constraints.
IC Wizard supports fully hierarchical design techniques, and can manipulate the logical/physical design hierarchy and map design constraints. The common timing engine and power router are already shared between the IC Wizard and Sonar/Dolphin, with complete database integration expected by the end of the year. IC Wizard was obtained through the acquisition of Aristo.
Monterey Design Systems - IC Wizard Screenshot (PicoJava Floorplan)
Monterey Design Systems - IC Wizard Screenshot (FPU Floorplan)
Sonar is a physical prototyping tool that enables users to perform early exploration, optimization, and analysis of design timing, routability, clock distribution, power distribution, and signal integrity. The Sonar tool shifts many of the detailed physical implementation tasks upstream, providing a physical prototype that is accurate enough to make design decisions without the extended runtimes necessary for a completed physical layout.
Both Sonar and Dolphin employ "continuous model refinement," which uses progressively finer grain models as the design process moves to completion. When implementation begins, only very course models are available to evaluate the timing and physical constraints. As implementation decisions are made, progressively finer grained models can be used until complete design closure is achieved and final masks can be generated. This reflects the natural progression of a complex design, with an increasing level of detail as the design proceeds from behavioral models to logical models and then physical models.
Monterey Design Systems - Sonar Screenshot (Multiplier Paths)
Monterey Design Systems - Sonar Screenshot (Clk Tree & Power)
Dolphin is a highly integrated physical design system that allows for the optimization of many different design parameters simultaneously. With modules for logic optimization, placement, signal routing, power routing, clock tree synthesis/routing, extraction, static timing analysis, signal integrity analysis and repair, Dolphin is indeed a complete physical design system. Rather than iterate thru a series of different tools for each task, Dolphin simultaneously optimizes the design to meet all the outstanding design constraints.
Monterey Design Systems - Dolphin Screenshot (PicoJava Layout)
Clive Maxfield did a good overview of the quadrisectioning technique used in Sonar and Dolphin in his April MaxBytes column, and I would recommend it as a basic introduction to the technique. As you can see from Figure 37 below, the quadrisectioning placement algorithm
continues to partition the design into finer and finer cluster and bin sizes until they are small enough to predict timing and congestion accurately.
As you can see from the above graphic, this technology also facilitates decomposition of design tasks for acceleration using multiple processors. Monterey's Global Design Technology algorithms employ a fine-grain multithreading architecture that can dispatch small tasks to the next available processor in a multiprocessor system. Each processor shares a single unified image of the design database.
This integral multiprocessor support provides a key performance advantage for the Sonar and Dolphin tools, as the tools can take advantage of 4, 8, 16, and 32(+) way SMP computer systems to accelerate design tasks. In the next part of this series I'll show how the use of "Parallel Environments" in the Sun Grid Engine (SGE) system can help manage the processor and computing resource requirements for running these tools on large EDA compute farms.
One of the most difficult problems facing physical designers today is meeting performance goals while maintaining sufficient safety margins for signal integrity issues such as crosstalk, IR drop, and electromigration. Dolphin addresses signal integrity issues simultaneously with the physical implementation to reduce the iterations required to achieve design closure. Dolphin's shape based, gridless and gridded router handles the routing requirements necessary for integrated crosstalk and electromigration avoidance.
Dolphin can generate a switching window and slew for each net, compiling a switching window density histogram that is used during placement to assign additional routing space between aggressor and victim nets in order to minimize crosstalk. The waveform calculator within Dolphin can capture the current density through each interconnect, as wires are placed and routed. The interconnect width and via count necessary to support that current density are automatically calculated so that additional routing resources can be allocated, if required, to meet the electromigration requirements of the particular technology.
Dolphin can also address the IR drop problem early in the design cycle, prior to the detailed placement. Power routing can have a large impact on cell placement, congestion, and signal routing paths, so early analysis is crucial to avoiding problems. Anyone who has had a min-cut placer drop all of their high powered buffers into the same row, because that minimizes the signal routing, knows the kind of problems that we're talking about here. Dolphin accumulates the cell power within a bin or region and represents this as a current source to the power grid, while a fast IR drop analyzer evaluates the IR drop so that the power grid can be sized automatically, with a graphical display.
Thermal Color Map depicts IR Drop Graphically
The combination of multiprocessor architecture support, new multithreaded algorithms, intelligent shaping and partitioning, and simultaneous global optimization with continuous model refinement will allow Monterey to give users high quality results in the minimum time required to achieve design closure.
Magma Design Automation
Magma Design Automation is the first EDA company to offer a complete, full-chip, hierarchical RTL to GDSII flow, based on a single unified in-memory data model.
Blast RTL is Magma's gain-based synthesis tool, and can synthesize a design without estimating cell sizing or fixing the implementation; this is left to be done after global routing, when more accurate load data is known. Blast RTL maps to the best topology required to implement the logic structure defined in the RTL. This strategy eliminates the need to define the gate-level representation of the design based on the inaccurate wire models used in more conventional synthesis tools.
Blast Plan is used for hierarchical design planning and floorplanning, and can partition large designs into more manageable-sized blocks. Using Magma's GlassBox abstraction technology for time budgeting of the chip-level timing constraints among the top-level blocks, each block can be implemented concurrently and then modeled as a GlassBox for full-chip extraction, timing analysis, clock tree synthesis and final assembly.
Blast Fusion is a complete netlist-to-GDSII chip implementation system that includes logic optimization, place and route, skew clock generation, floorplanning and power planning, RC extraction, and an incremental timing analyzer.
Diamond SI is Magma's standalone verification system for sign-off verification of signal integrity problems such as crosstalk noise and delay, IR drop, and electromigration on signal nets and power rails. Diamond SI includes a 3D parasitic extraction engine as well as an embedded static timing analysis engine. It also includes a SPICE interface for lining to transistor-level simulators.
Because Magma is a complete system, the learning curve for the system is steeper than simply plugging a new point tool into an existing design flow. I think that this is one of the reasons that the Magma tools have been slow to be accepted by some designers. As I get several of the example designs completed through the entire Magma tool suite, I'll report in more detail on the time required to come up to speed with their entire flow, and the results obtained on the example designs.
In this series I've outlined some of the design flows in use today, starting with RTL exploration in Parts 1 and 2, RTL synthesis in Part 3, and physical optimization, layout and signal integrity analysis in Part 4.
Coming next in Part 5
In the final installment of this series I'll demonstrate several techniques for the integration and automation of these RTL to GDSII design flows. I'll discuss several ways to reduce your design cycle turnaround times, using resource management tools like the Sun Gridware Engine, as well as some of the advanced dependency graphing tools, such as Flowtracer/EDA.
Tom Moxon is the founder of Moxon Design, an electronics design consulting organization. He has designed integrated circuits for client companies, including Cray Research, Adobe Systems, Hewlett Packard, Silicon Graphics, Rohm, and Hyundai Electronics. Tom has been working for several years on web enabling EDA and CAD infrastructures, and is researching EDA applications using XML/XSLT, RDF, DAML, and XML-RPC. When he's not "slinging gates" for a living, Tom is often called upon to torture test new EDA tools before they are inflicted on the remainder of the engineering community.