A clear understanding of design-integrity issues and the ability to control related problems are prerequisites for first-time success in silicon. With narrow margins for ultradeep-submicron (UDSM) technology, high-yield designs can no longer be produced without considering design-integrity effects.
Design-integrity challenges today are not limited to meeting timing constraints. With finer line widths, longer interconnects, lower power supply voltages and higher clock frequency, deign-integrity issues include crosstalk noise, power dissipation, power net voltage drop and signal and power net electromigration.
Design-integrity concerns need to be addressed early in the design phase in order to best achieve design closure. Concurrent optimization is extremely important because design-integrity issues are interrelated-they occur simultaneously and affect each other. For example, voltage drop on power nets affect timing and crosstalk noise; on the other hand, voltage drop itself is determined by how fast gates are switching.
UDSM design rules allow on-chip geometries to be routed very closely to each other, allowing for high packing density. However, close proximity of interconnects can cause unintentional switching, slowdown or speedup of a neighboring node, or victim, during intentional switching of a given node, or aggressor. These may produce functional or timing failures.
Five electrical parameters determine the magnitude of these crosstalk effects: the coupling capacitance between interconnects; the driver strength of victim and aggressor nets; the relative switching interval; the total capacitance of interconnect; and the interconnect resistance.
Not every noise glitch in a design leads to chip failure because the built-in noise immunity of digital circuits comes to the rescue. A functional failure due to noise can happen only if the noise pulse can propagate through the circuit, and get latched on to a register element (flip-flop or latch). This is true for static CMOS design. In dynamic logic circuits, however, if the noise pulse has enough energy to switch the next stage, functional failure may happen. The energy of noise pulse is measured by the height and the width of the noise pulse.
A design that meets timing demands without considering crosstalk-induced delay could still fail in silicon. Generally, crosstalk-induced delay changes the critical path of a timing-optimized design; paths whose timings are close to the critical path are most susceptible to become the new critical path.
Any technique to alleviate crosstalk-related problems must control one of the five factors mentioned earlier. A few of the commonly used techniques are: to increase spacing between interconnects; reduce the length of interconnects by buffer insertion; size buffers to change the driving strength of victim and aggressor net drivers; and avoid routing long parallel nets and routing nets with overlapping timing windows away from each other. To achieve design closure, these techniques must to be used at early stages of physical design.
With smaller geometries in UDSM processes, gate density and total number of gates are increasing rapidly, as are power density and total power. There are three major components of power dissipation: switching power, short-circuit power and leakage power. Switching power is the power consumed to charge or discharge device and interconnect capacitance, and its value depends on the frequency of switching, the total capacitance to be charged or discharged and the power supply voltage. Short-circuit power depends on the slew rate, the device characteristic (saturation current) and power supply voltage. Leakage power has two contributors-the current flowing through the reverse-biased diode junctions of transistors and the subthreshold currents of MOS transistor.
Switching power is the most important contributor to the total power. To keep the total power consumption at a reasonable level, power supply voltage is continuously scaled down, with increasing total gate count and gate density. However, power-supply voltage scaling affects performance, so it can't be lowered indefinitely. To increase drive strength, designers have tried to lower the threshold voltage of MOS transistors. Lowering the threshold voltage implies an exponential increase in the subthreshold current, however, and hence the leakage power. In UDSM technology, the higher contribution of leakage power to total power is already a cause of concern. Clearly, there is a strong trade-off between performance and power dissipation of a design.
Foundries offer dedicated low-power processes for certain applications. UDSM designers also need to use low-power design techniques to achieve the best performance-vs.-power trade-off. Such techniques include partitioning designs into multiple voltage domains to reduce switching power; shutting off power to certain portions of the chip to reduce leakage of power; using standard cells with multiple threshold voltages; switching off, or "gating," the clock when a certain section of the circuit is inactive; and optimizing the clock tree and critical paths to remove unnecessary buffers. These techniques need to be used throughout the design process.
Power rail voltage drop
The effective power supply voltage of a standard cell is always less than the ideal supply voltage. The drop in power supply voltage, called voltage drop or IR drop, occurs because of the current flowing through the resistive power network. Its value depends on the resistance of the power net, power grid architecture, power pad locations and the current drawn by standard cells connected to power net. Power net voltage drop affects the performance of a design with increased cell and interconnect delay. It also reduces noise margins of cells and increases the chance of chip failure due to crosstalk noise.
It is important for designers to have knowledge of both average and peak current drawn from the power net for accurate analysis and optimization of voltage drop. Calculating voltage drop based on average current helps with design and optimization of the power grid, but the voltage drop calculated in this fashion is not the worst-case voltage drop. Worst-case voltage drop calculation requires knowledge of peak current, switching characteristics of the design and parasitic capacitance and inductance of the power net. Accurate voltage drop analysis should also take into account impedance of off-chip wiring.
The voltage drop problem is a global effect. If a certain region of a design contains excessive voltage drop, it can't be resolved by a quick fix of that particular region. Instead, it will require a fix somewhere else, such as by changing the number of straps of the power mesh. As with all other design-integrity issues, this needs to be addressed early in the physical design process. With an estimate of power consumption in hand, various power network architectures should be evaluated and, finally, optimized to obtain the power network with the most uniform and lowest voltage drop. Placement optimization should include insertion of decoupling capacitor cells to reduce peak IR drop. The optimization techniques employed need to be tuned to the packaging technology (flip-chip or wire-bond) that determines location of power pads.
Electromigration is a reliability issue that determines the useful lifetime of a chip. As a result, UDSM designers need to reduce the probability of electromigration and increase the reliability of their designs.
Electromigration is caused by the dislocation of metal ions from lattice structures by fast-moving electrons. This causes the wire to break or to short-circuit to another wire. In either scenario, a functional failure may occur, rendering the chip useless. The rate of electromigration depends on the current density, the temperature and the crystal structure of metal. These factors are incorporated in an empirical equation (Black's equation) to calculate mean time-to-failure of a design. One of the advantages of copper technology is a lower probability of electromigration.
To reduce the rate of electromigration, UDSM designers should have control of peak, average and RMS current density. Interconnects with currents flowing in one direction are more susceptible to electromigration than those with bidirectional current flow. The power nets and the pieces of signal net with unidirectional current flow, such as pull-up transistors, are most vulnerable to electromigration problems. Foundries provide two different sets of electromigration rules, AC and DC, to differentiate these two cases.
In UDSM technology, signal electromigration is becoming an area of concern for designers. With finer line widths in UDSM processes, the current density on the bidirectional signal nets can easily exceed the AC thresholds. Standard cell placement and signal routing need to take this effect into account, along with crosstalk and timing.
During synthesis and optimization of power grid, electromigration should be evaluated along with voltage drop. UDSM designers should be careful about insufficient number of vias in a power rail and narrow power trunks to avoid power net electromigration.