By Wolfgang Roethig, Senior Engineering Manager, NEC Electronics Inc., Santa Clara, Calif., Vassilios Gerousis, Design System Architect, Infineon Technologies AG, Munich, Germany, Rajit Chandra, Chief Technology Officer, Magma Design Automation Inc., Cupertino, Calif., and Vic Kulkarni, Chief Executive Officer, Sequence Design Inc., Santa Clara, Calif.
Many of the challenges facing EDA tool users graduating to ASIC-style system-on-chip (SoC) design at 0.13 micron and below can be addressed through the use of new methodologies taking advantage of the Advanced Library Format (ALF). These new design techniques concurrently analyze and optimize timing, crosstalk, power, noise, electromigration, and hot-electron constraints based on accurately characterized ALF cell libraries.
In the past, ASIC design has focused almost exclusively on timing closure. Guardbands were used to protect signal integrity from noise, electromigration, and other adverse effects. As technology-feature sizes continue to shrink, and more functionality is implemented on chip by using more routing layers, power consumption and noise reach unprecedented levels.
An integrated approach is necessary, since timing closure and functional verification signoff are not accomplished until post-layout signal integrity effects have been dealt with. Point tools are unable to manage the relationships among crosstalk, power, and other ultra-deep submicron (DSM) physical effects simultaneously.
For example, point tools for signal integrity analysis are applied after place-and-route. They uncover signal integrity violations and generate scripts for buffer /insertion/deletion/resizing, for placement changes, or for routing changes, but the drawback is that place-and-route is not completely controlled by these scripts. So, after repairs are made, signal integrity has to be rechecked. And, since signal-integrity checking tools do not know the timing, the repairs can often conflict with timing constraints.
An analysis-driven design optimization flow tackles signal integrity concurrently with timing closure. Point tools act on these issues independently with no shared knowledge of the problems they are attempting to address. ALF libraries providing highly accurate characterization models of timing, noise, electromigration, and power that can be understood by all the pertinent tools in the flow are the best hope the industry has today for the creation of a credible and highly accurate analysis-driven flow.
Creation of a standard
The ALF standard began with the OVI Power & Synthesis Technical Steering Committee (PS-TSC) early in 1996, which had the charter to define a standard library data format for synthesis and power analysis/optimization. After the release of ALF 1.0, the scope was extended to cover signoff-worthy timing and signal integrity as well as physical design. The overarching goal was to provide a forward-looking standard to cover comprehensive functional, electrical and physical modeling of technology, standard cells and blocks. ALF 2.0 today is Accellera approved and an emerging IEEE standard (P1603), and fast gaining notice as an idea addressing the right design problem at the right time, just as Verilog, VHDL, SDF, SPEF and others have done before.
The success of the analysis-driven flow relies on signoff-accurate libraries. A suite of benchmarks with normative Spice results has been applied to qualify the ALF library within the context of its usage in such a flow. For example, the ALF timing library alone, by virtue of including more precise data, yields significantly better accuracy than a conventional timing library.
For very deep submicron designs, the shape of the signal waveform plays a significant role in describing the timing characteristics. A driver-resistance model handles both waveform shape and susceptibility to noise. Eventually, multiple signals on coupled nets switch simultaneously and cause mutual waveform distortion. The use of driver resistance models allows designers to calculate the resulting waveforms using linear circuit analysis.
The resulting waveforms depend also on the alignment of the original waveforms. If pessimistic time windows are used, the waveform alignment is not known with much certainty. Therefore, the concept of activity windows is introduced. The idea is to calculate multiple narrow time windows of possible switching activity per clock cycle to decide with more certainty, whether aggressor and victim waveforms will overlap .
Each activity window is associated with bounds for output arrival time, slew rate, and driver resistance. These parameters are calculated from input arrival times and slew rates, using timing models in the ALF library. The particularity of an ALF model is its association with a symbolic waveform, represented as a vector. This allows a one-to-one correspondence between characterization specification and resulting timing model.
Driver resistance for steady state is used for noise calculation on a quiet victim driver. In addition, a noise margin on a victim receiver must be provided to decide whether the noise can be tolerated. The definition for noise margin implies that the noise activity at the output due to the noise at the input is negligible. For combinatorial cells, noise activity at the output can be tolerated, as long as it does not corrupt the data of a memory element, a flip-flop or a latch.
Therefore, noise propagation instead of noise rejection can be described in the library, and demonstrates that noise analysis is a natural extension to timing analysis. This extension requires additional characterization data that can be well described in ALF. Noise waveforms are a derivative of signal waveforms. The latter are described by slew rate, the former are described by pulse width and noise.
Electromigration (EM) occurs inside cells as well as on interconnect structures. Electromigration is due to high current density, which eventually causes wires and contacts to break. These effects can be characterized by transistor-level transient current and voltage simulations. The resulting models can be represented in an ALF library as well. ALF supports description of average, RMS, and peak current data. This data can be associated with technology, with a pin in a cell model, or with a node of a wire model. Customized models for current measurements, such as the "effective" current which models self-healing in the case of AC electromigration, are also supported.
The hot-electron (HE) effect occurs also inside a cell. During the lifetime of an NMOS transistor, its switching threshold is gradually changed due to the HE effect, until the transistor no longer meets the performance spec. More recently, the thermal instability effect is also a cause of concern. This effect degrades the performance of a PMOS transistor over the span of its lifetime.
For complex cells and blocks, the electrical data can be abstracted using the ALF vector concept. An ALF vector defines the activation stimulus for a path within a cell or a block. Associated with the vector is an upper limit for tolerable activation frequency of the vector. This frequency limit is an abstraction of the tolerable EM or HE damage, which depends on either input slew rate and output load or both.
Since ALF vectors can contain temporal and logical dependencies, it is possible to represent electromigration and hot-electron constraints affecting internal structures of a complex cell by vector frequency limits describing events and states observable at the boundary of the cell. Even tools working on a purely functional level, such as RTL simulation, can handle this degree of abstraction. This opens the prospect of preventing EM, HE and eventually thermal instability effects at a very early stage of high-level design. However, at the physical design stage, EM and HE have to be re-evaluated using the same model, but more accurate slew rates and layout parasitics.
With a point-tool approach, noise, EM and HE effects are checked individually and eventually fixed through manually or automatically generated scripts prescribing incremental layout changes. The point tools are mutually unaware of other effects, therefore the fixing of an electromigration violation may cause timing violations.
Anticipating problems early
The new methodology described here applies to physical design tools, which are conscious of timing, noise, EM and HE. In the physical synthesis, placement optimization and routing stage, many problems can be anticipated and avoided. Noise-aware buffer insertion can break up coupling capacitance. Additional features are noise-aware gate sizing to reduce violations, noise-constrained tracking, signal-shield wire routing, and track reordering based on timing windows.
However, not all problems can be 100 percent avoided, since accurate parasitics are only known after full layout implementation. At that stage, timing, noise, EM and HE are re-evaluated with signoff accuracy. In a traditional flow, manual engineering change order (ECO) would be done based on the remaining violations. In the new flow, the signoff analysis and ECO capability are integrated in the same post-route optimization tool. The tool implements only design changes with minimal disturbance, such as buffer resizing or buffer insertion along existing routes. As a result, the number of design iterations is greatly reduced. No intermediate SDF files are necessary for ECO.
As with any design flow, external system-level timing constraints must be provided. Noise and EM/HE constraints are provided as noise margins and vector-frequency limits, respectively, in the library. In addition, a global activity file (GAF) is provided for EM/HE analysis. This file contains estimated or simulated vector-frequencies for each cell instance within the design, which must be checked against the vector frequency limits in the library.
For a given vector frequency, the slew and load-dependent frequency limit translates into a slew-dependent load limit. Since the design transformations done by the physical synthesis or optimization tool are restricted to insertion, removal, or substitution of local buffers and cells, the GAF for the initial netlist can serve as a reference throughout the flow.
Further enhancing the flow is the addition of power-analysis tools, also using ALF, which analyze and help designers deal with power and energy issues from the architectural level to physical design. Since power consumption depends on power vector activity, the GAF can be used in the power analysis flow as well.
Circuits with very high power consumption exhibit significant thermal gradients across the chip. This is problematic because conventional timing analysis assumes a single temperature for the entire device, even though it is well known that timing is temperature dependent. The usual response is simply to minimize overall chip temperature through the use of more sophisticated, and expensive, packaging.
Reducing supply voltages while boosting clock speeds into the gigahertz range pushes thermal densities off the charts. Managing these issues simultaneously calls for the creation of a power signoff standard for nanometer-scale chips.
Power signoff verifies that power and current specs are accurate, and that delay and noise impacts caused by power are accounted for and fixed. For example, once the time-averaged power has been calculated, its values can be used to determine junction temperatures and thermal gradients, and these instance-specific junction temperatures can be used to more accurately calculate delays. These same temperature values can also be used to evaluate reliability parameters such as electromigration limits since they, like delay effects, are highly sensitive to temperature.
New design tools must model complex electrical effects based on the interactions of resistance, capacitance, and inductance, while analyzing designs in their entirety since the effects caused by power are interdependent throughout the power grid. Particularly important is a power modeling capability utilizing the rich syntax and versatility of ALF that facilitates the creation of high-quality power models for complex IP blocks.
As part of the concurrent analysis and optimization flow, power analysis tools implemented during RTL development permit design alternatives and power tradeoffs to be explored, such as partitioning to account for multiple voltage sources.
Following synthesis, design optimization includes steps such as power gating limiting power in different areas to reduce leakage currents. This permits the power grid to be completed prior to layout using a correct-by-construction approach rather than the ad hoc approach used today. Next, the designer produces a placement which provides first-order timing data an initial indication of delay that will occur in the interconnect structures of the design. During post-placement optimization the designer can reduce power by using techniques such as "high threshold cells," placed in areas where timing is not critical. They do not alter the timing of critical paths but reduce leakage in non-critical paths.
Routing completes the process, followed by final verification. At this point thermal gradients and infrared (IR) drop data are calculated. With this information the designer can determine if the circuit meets timing, power, thermal and noise specifications prior to completing the power signoff.
It has become apparent that a new design flow with a greater level of integration of tool functionality and library is required for ultra-DSM SoCs at 0.13 micron and below. Analysis-based optimization for timing, signal integrity, reliability, and power can be accomplished today with commercially available tools in a unified flow, providing a common analysis backplane, using signoff-worthy ALF models.