Editor's Note. To view a PDF version of this article, Click Here.
The drive to integrate an entire transceiver on a single chip has spurred a host of technical challenges arising from the myriad complex interactions among various sections of that system, particularly at the RF end. To overcome those issues, today's RF designer needs expertise in communication and signal theory and must make intelligent trade-offs among such critical parameters as noise, power, gain and linearity.
Designers must therefore have in their arsenals powerful and well-integrated EDA software that can not only simulate each subsection of the RFIC but also accurately simulate overall chip performance for verification against wireless standards. That software must be capable of incorporating more recent, advanced techniques for nonlinear circuits with complex modulated RF signals, while also factoring in the ever-increasing size of the RF circuits.
A typical RFIC in a wireless communication product has performance parameters that must be simulated at the system level (adjacent-channel power ratio, or ACPR), at the subsystem level (spurious-free dynamic range, or SFDR), at the component level (phase noise) and sometimes at multiple levels (ACPR for the power amplifier and for the entire RF transmitter). Because of those requirements, no single simulator can provide all performance measures. In addition, the architectural, subsystem and component-level simulations of both the analog/RF and baseband portions of the system should not be done in isolation. Well-known techniques to achieve whole-system simulation range from dc simulation to harmonic-balance simulation.
Dc simulation: Calculating the dc operating point of a circuit is a prerequisite for other simulations such as ac, transient and harmonic balance. In dc simulation, ac sources are ignored, capacitors are replaced with open circuits and inductors with short circuits, and nonlinear devices are represented by their Spice models. The simulator uses the Newton-Raphson algorithm to solve Kirchoff's Current Law (KCL) at each node.
Ac and S-parameter simulations: Ac and small-signal S-parameter simulations first establish the dc operating point. Then nonlinear devices are linearized around their dc operating point by assuming that the ac source levels do not perturb the dc operating point. Linear devices are represented by their small-signal frequency-domain Y or S parameters. That allows accurate frequency-domain models for distributed components to be included in the analysis. After each device is represented by its linear model, the Y or S matrix of the overall circuit is calculated at its external ports.
Transient time-domain simulation: Transient simulation is appropriate for such applications as large baseband circuits, startup transients and oscillators. Here, dc bias analysis is performed. Nonlinear devices are represented by Spice models; linear devices are represented by their lumped-equivalent circuits. Frequency-domain distributed models are either represented by their Y or S parameters or by rational polynomials.
Finite-difference calculation is used on each circuit node current to convert the system of differential equations to a system of algebraic matrix equations.
This system of equations is then solved in an iterative manner using the Newton-Raphson algorithm such that KCL is satisfied at each circuit node.
The transient time-domain simulation is typically performed at both the component and chip levels. The final verification of an RFIC includes a transistor-level transient simulation of the whole IC. However, computation time and memory constraints associated with transient time-domain simulation have created the need for other simulation technologies, which will be discussed later.
The convolution simulator: This is an extension to the transient simulator. It allows simulation of frequency-domain models such as microstrip and strip lines in time-domain simulators and also accounts for high-frequency effects such as skin effect and dispersion.
Convolution works as follows: A finite input response (FIR) convolution is performed on distributed models by converting their frequency-domain S or Y parameters to impulse responses and then convolving the input waveforms with the impulse responses. For frequency-domain models that can be represented accurately using a Laplace or a rational polynomial model, recursive convolution is used. This is faster and numerically more stable than the FIR convolution.
Neither the S-parameter technique nor the transient time-domain technique is applicable to the steady-state solution of nonlinear circuits with multitone excitation. The S-parameter technique is a linear simulation technique, while the transient technique is not practical for multitone excitation with closely spaced tones. The solution is a frequency-domain nonlinear simulator called the harmonic balance (HB) simulator.
RFICs typically include frequency up- and/or down-conversions. HB is the ideal technique to analyze systems with multiple, closely spaced independent signals. Linear distributed models can be accurately modeled at the same time, because HB is a frequency-domain technique.
Nonlinear noise analysis is another unique capability of HB. Spice linear noise analysis cannot predict the noise performance of a circuit with frequency-mixing effects or determine nonlinear responses to variations in input signal amplitude, such as gain compression. HB can accurately simulate nonlinear noise of mixers and oscillators, including their large-signal effects.
Finally, HB is most useful in the analysis of components or systems that involve intermodulation distortions (IMD) and/or frequency-conversion. Examples include mixer IMD with closely spaced tones, power amplifiers, load-pull, frequency multipliers, steady-state response of oscillators and system simulation.
The harmonic-balance solution process begins by performing a dc simulation to obtain the dc operating point. The periodic excitation signals are represented by Fourier series with a finite number of harmonics of each independent tone. Initially, an estimate is made for the voltage spectrum at each circuit node. That spectrum is converted to a time-domain voltage waveform using an inverse FFT. Time-domain current waveforms at the nonlinear device terminals are computed using their Spice models and the voltage waveforms. The time-domain currents are then converted to a current spectrum at each terminal using FFT. The current spectrum at each linear device node is computed from S or Y parameters and the voltage spectrum at each node. That provides a first-iteration current spectrum at each circuit node. The estimated initial voltage spectrum is then adjusted to satisfy KCL at each node. This Newton-Raphson iterative process continues until the difference between the two successive iterations drops below a predetermined threshold.
Krylov subspace solver
With the Newton-Raphson technique that HB simulators use, each iteration requires an inversion of the Jacobian matrix associated with the nonlinear system of equations. When the matrix is factored by direct methods, memory requirements climb as O(H2), where H is the number of harmonics.
An alternate approach to the solution of the linear system of equations associated with the Jacobian is to use a Krylov subspace iterative method such as generalized minimum residual (GMRES). This method has a memory requirement proportional to O(H), not O(H2), in the context of harmonic balance. Thus the Krylov solver saves on memory requirements for large harmonic-balance problems, with a corresponding increase in computation speed. This speed makes it practical to use HB for full-chip simulation with multitone excitation.
CCT envelope simulation
Unlike traditional communications designs involving sinusoidal modulations, modern wireless applications employ more sophisticated digital RF modulation for more efficient spectrum usage. These include pi/4 differential quadrature phase-shift keying (DQPSK) and QAM, as used in wideband CDMA (W-CDMA), Edge and GSM standards. Associated with these modulation schemes are new RF specifications, such as ACPR, error vector magnitude (EVM) and NPR. In addition, components such as phase-locked loops (PLLs) and automatic gain controls (AGCs) must satisfy tight timing specifications for frequency-and power-level settling, respectively.
Circuit envelope (CE) was developed specifically to provide an efficient simulation technique for transient and complex modulated RF signals. Unlike Spice, it samples the baseband modulation envelope of the signal instead of its RF carrier. The RF carrier is simultaneously computed in the frequency domain for each envelope time sample. The output is a time-varying spectrum.
CE efficiently analyzes amplifiers, mixers, oscillators and feedback loops in the presence of modulated and transient high-frequency signals, allowing the efficient and accurate analysis of the sophisticated signals found in today's communication circuits and subsystems. This simulation technology combines the advantages of time- and frequency-domain techniques to overcome the limitations of harmonic balance and Spice simulators in such applications.
At the architectural level, designers are interested in the entire system performance, from "bits in to bits out." The measurements of interest are the overall bit error rate (BER), EVM, etc., which are closely related to the performance of the baseband sections of the system.
Simulation of behavioral DSP designs in conjunction with analog/RF circuit designs is critical to the success of the integrated components, devices and subsystems used in wireless modems. Verification of the impact of real-world analog/RF issues on the DSP algorithms, and vice versa, is vital in making intelligent choices in the trade-offs between performance and circuit complexity.
Today's designs use a mix of analog/RF and dedicated on-chip baseband blocks, and they require high levels of integration at the boundary between the two environments. Co-simulation between baseband and RF circuits addresses that need. A design environment that supports a mix of simulation engines, signals and models, supporting baseband, RF and analog technologies, provides great value for both top-down system specification and bottom-up test and validation.
Timed asynchronous data flow signal-processing simulators provide the bridge between baseband simulation and RF circuit simulators, enabling end-to-end communication system simulation for specifications.
Many recent improvements in technology have resulted in greater simulation efficiency and robustness. Both time- and frequency-domain simulators can now solve very large and nonlinear RF circuits. To solve the nodal KCL equations, a set of equations and the associated Jacobian matrix is usually constructed and solved. In circuits with many nodes and harmonics, this matrix tends to get very large and complex. This is when Krylov subspace solvers become very useful. But if the circuit is also highly nonlinear with many complex off-diagonal terms in the matrix, even the Krylov subspace solver encounters difficulty. A robust preconditioner is needed to simplify and approximate that matrix to allow the Krylov subspace solver to obtain the final solution.
Two new preconditioners have been developed in addition to the standard Krylov dc preconditioner (DCP). These are the block-select preconditioner (BSP) and the Schur complement preconditioner (SCP). The dc preconditioner works well for most circuits, but it is not effective on highly nonlinear circuits. The BSP, which adds further nonlinear blocks to the DCP, ensures robust convergence on highly nonlinear circuits. The BSP uses block selection: It divides the Jacobian matrix into a set of linear and a set of nonlinear blocks, where the nonlinear blocks correspond to the most nonlinear parts of the circuit. Using the BSP will produce convergence at the cost of additional memory usage.
The Schur-complement preconditioner is used for the most strongly nonlinear circuits (Figure 1). While the DCP uses a dc approximation on the entire circuit, the SCP partially applies that approximation, excluding the most nonlinear parts. Applying SCP requires a more complex sequence of steps that includes an internal Krylov solve at each iteration of the outer Krylov loop. So using SCP is typically more expensive in terms of memory usage. The addition of a specialized Krylov solver for the SCP improves memory usage and has resulted in improved speed and efficiency.
Comparing the two new preconditioners, BSP is a simpler technology than the SCP technology. Sometimes, it is faster than SCP. But in cases where the nonlinear part of the circuit is larger (as determined by the nonlinear column selection), BSP will start to use a lot of memory and becomes inefficient. This is where SCP becomes more useful.
The size of the problem in harmonic balance depends on the number of equations (which is related to the number of devices and nodes) and the number of frequency harmonics. For a circuit with one tone, the problem size is equal to the total number of equations per frequency, multiplied by [(2 * # of harmonics) - 1].
To prove out the new preconditioners, a test was done on a bipolar frequency divider circuit with 133 devices, including 48 nonlinear devices. The number of frequencies (harmonics) was increased from eight to 512 to increase the nonlinear problem size for the HB Krylov solver. The default dc preconditioner was not able to solve the matrix. BSP and SCP were used, and their results are outlined in Figure 2.
Note that the BSP resulted in faster simulation and consumed less memory with a smaller problem size. With larger problems, the SCP surpasses the BSP's speed and overall memory performance.
Transient-assisted harmonic balance (TaHB) is another technique that has been used successfully to ensure convergence and solution on very large and highly nonlinear circuits, such as flip-flops in PLL ICs as well as ring oscillators. The transient simulator is run until steady state is reached, then the transient solution is applied as an initial estimate in Krylov HB and its preconditioners.
No single simulation technology can address all the simulation needs in an RFIC. All the simulation technologies we've described should be tightly integrated into a single environment that lets the designers do a top-down multilevel co-simulation using different levels of model abstractions.
Author's Note: The author's would like to take this opportunity to acknowledge David Long and Bob Melville for their work in inventing the SCP preconditioner.
About the Authors
Jack Sifri is Agilent EEsof EDA's product manager for RFIC simulation. He has a BSEE and MSEE from UCLA and an MBA from the University of Southern California. Jack can be reached at firstname.lastname@example.org
Niranjan Kanaglekar is R&D section manager for RF/mixed signal at Agilent EEsof EDA. He has a BEEE from the College of Engineering, Pune, India, and an MSEE and PhD from the Univ. of Massachusetts at Amherst. Niranjan can be reached at email@example.com.