SAN MATEO, Calif. Eschewing the shared bus approaches favored by ARM and PowerPC cores, MIPS Technologies Inc. has introduced an on-chip switch for system-on-chip developers. Called SoC-it, the switch is intended to provide a high-performance link between a MIPS processor and multiple third-party intellectual property cores.
ARM Ltd. was one of the first companies to respond to the need for a standard system-chip interconnect when it released its Amba on-chip bus; IBM Microelectronics followed with its own shared bus for the PowerPC dubbed Core Connect. MIPS hopes to leapfrog both efforts with a higher-performance switched interconnect especially geared for designers in its key media-centric markets for such systems as set-top boxes, videogames, networking systems and office automation equipment.
Rather than introduce a new core interface for MIPS users, the company is rolling the on-chip switch together with a memory controller and dual-ported intellectual-property interface logic, including an Amba and PCI bridge controller. Existing third-party cores can plug into either bridge interface or into SoC-it's IP interface which is similar to the existing MIPS processor bus.
Ken Yap, a product marketing manager at MIPS, said the cost of a SoC-it license will be less than $150,000 the current cost of buying a third-party double-data-rate memory controller and PCI bridge core.
"We saw opportunity to do switched interconnect for better performance at lower cost while maintaining our IP interface," Yap said. "This is a set of system-level blocks that let users differentiate designs while remaining bus-agnostic. It preserves their investment in their IP and provides them a migration path."
MIPS provides SoC-it as register-transfer level code. Prices vary by configuration, processor type and usage model, with one-time use and limited three-year and five-year licenses available. SoC-it is available now and MIPS said it already has four users, one in each of its primary markets, but has not announced their names.
"This could go a long way to addressing power concerns for portable systems," said Tony Massimini, chief of technology at market watcher Semico Research (Phoenix). "Any system where power and board size are issues could benefit from this, and I don't think it will compete with standalone cores."
MIPS estimates that SoC-it will require from 119,000 to 155,000 logic gates in a 0.18 micron process at Taiwan Semiconductor Manufacturing Co., depending on whether users implement it for the 4K, 5K or 20K MIPS processor. The on-chip switch comes in configurations sporting throughput from 1.06 to 4.24 Gbytes/second.
The company estimates the SoC-it switch provides a 20 percent average performance boost over a standard MIPS design when implemented in a discrete FPGA, and higher when implemented in a full ASIC-style system-on-chip design.